公开(公告)号：US11307854B2

公开(公告)日：2022-04-19

申请号：US15891028

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Roman Dementiev ,  Vadim Sukhomlinov

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.

公开(公告)号：US10268502B2

公开(公告)日：2019-04-23

申请号：US15637476

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Vadim Sukhomlinov ,  Roman Dementiev

IPC: G06F9/46 ,  G06F12/0831 ,  G06F9/30

Abstract: A method to perform atomic transactions in non-volatile memory (NVM) under hardware transactional memory is disclosed. The method includes tracking an order among transaction log entries that includes arranging transaction logs in an order that is based on when corresponding transactions were executed. Moreover, the method includes, using the ordered transaction logs to recover data states of the nonvolatile memory, by identifying a first unconfirmed transaction associated with a transaction completion uncertainty event based on a corresponding one of the transaction logs including a first commit marker but not including a confirm marker, undoing first ones of the transactions in reverse time order starting at a last transaction that recorded a second commit marker, up to and including the first unconfirmed transaction that recorded the first commit marker, and redoing second ones of the transactions in forward time order from a first confirmed transaction up to but not including the first unconfirmed transaction that recorded the first commit marker.

公开(公告)号：US09384148B2

公开(公告)日：2016-07-05

申请号：US14367989

申请日：2013-12-17

Applicant: Intel Corporation

Inventor： Igor Muttik ,  Roman Dementiev ,  Alex Nayshtut

IPC: G06F21/14 ,  G06F12/14 ,  G06F21/60

CPC classification number: G06F12/14 ,  G06F12/1441 ,  G06F21/53 ,  G06F21/54 ,  G06F21/566 ,  G06F21/60

Abstract: Technologies for detecting unauthorized memory accesses include a computing device having transactional memory support. The computing device executes a code segment identified as suspicious and detects a transactional abort during execution of the code segment. The computing device may execute a security support thread concurrently with the code segment that reads one or more monitored memory locations. A transactional abort may be caused by a read of the security support thread conflicting with a write from the code segment. The computing device may set a breakpoint within the code segment, and a transactional abort may be caused by execution of the code segment reaching the breakpoint. An abort handler determines whether a security event has occurred and reports the security event. The abort handler may determine whether the security event has occurred based on the cause of the transactional abort. Other embodiments are described and claimed.

Abstract translation: 用于检测未经授权的存储器访问的技术包括具有事务存储器支持的计算设备。 计算设备执行标识为可疑的代码段，并且在执行代码段期间检测事务中止。 计算设备可以与读取一个或多个监视的存储器位置的代码段同时执行安全支持线程。 事务中止可能是由安全支持线程读取与代码段的写入冲突引起的。 计算设备可以在代码段内设置断点，并且可能由执行到达断点的代码段引起事务中止。 中止处理程序确定是否发生安全事件并报告安全事件。 中止处理程序可以基于事务中止的原因来确定安全事件是否已经发生。 描述和要求保护其他实施例。

公开(公告)号：US10146538B2

公开(公告)日：2018-12-04

申请号：US15282011

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Roman Dementiev ,  Ravi Rajwar ,  Ady Tal ,  Alex Gerber

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F12/0855 ,  G06F12/123 ,  G06F12/0875 ,  G06F9/46 ,  G06F9/38

Abstract: Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

公开(公告)号：US20180004521A1

公开(公告)日：2018-01-04

申请号：US15200676

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Andreas Kleen ,  Raanan Sade ,  Ahmad Yasin ,  Ravi Rajwar ,  Robert S. Chappell ,  Roman Dementiev

IPC: G06F9/30 ,  G06F12/0815 ,  G06F3/06 ,  G06F12/084

CPC classification number: G06F9/30043 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/3834 ,  G06F11/30 ,  G06F12/0815 ,  G06F12/084

Abstract: A method of analyzing aborts of transactional execution transactions. Starting a transactional execution transaction with a first logical processor. Performing, with a second logical processor, store to memory instructions, while the first logical processor is performing the transactional execution transaction. Capturing memory addresses of, and instruction pointer values associated with, at least a sample of the store to memory instructions. Performing, with the second logical processor, a first store to memory instruction to a first memory address, which is to cause the transactional execution transaction to abort. Capturing the first memory address. Determining an instruction pointer value associated with the first store to memory instruction by correlating at least the captured first memory address with the captured memory addresses of said at least the sample of the store to memory instructions.