公开(公告)号：US11489061B2

公开(公告)日：2022-11-01

申请号：US16139248

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dusgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.