公开(公告)号：US20240222274A1

公开(公告)日：2024-07-04

申请号：US18147820

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Sivakumar Nagarajan ,  Nisha Ananthakrishnan ,  Santosh Shaw ,  Wei Gao

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06541

Abstract: Integrated circuit (IC) dies, microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, an IC die may include a substrate, a front-end-of-line (FEOL) layer over the substrate, where the FEOL layer includes a plurality of transistors, a first back-end-of-line (BEOL) layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects.