公开(公告)号：US20170170088A1

公开(公告)日：2017-06-15

申请号：US15037851

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Venmathy McMahan ,  Sivakumar Nagarajan ,  Elah Bozorg-Grayeli ,  Amrita Mallik ,  Kuang-Han Chu ,  Liwei Wang ,  Nisha Ananthakrishnan ,  Craig J. Weinman ,  Amram Eitan

IPC: H01L23/29 ,  H01L23/18 ,  H01L23/31

Abstract: Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

公开(公告)号：US20160240395A1

公开(公告)日：2016-08-18

申请号：US15139265

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L24/13 ,  H01L2224/16225 ,  H01L2224/29647 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括用硫醇粘合促进剂，唑偶合剂，表面改性填料和基于过氧化物的交联聚合物化学物质之一改性底部填充材料，以便利用本文的实施方案极大地增强包装结构中的粘合性。

公开(公告)号：US09245815B2

公开(公告)日：2016-01-26

申请号：US14265199

申请日：2014-04-29

Applicant: INTEL CORPORATION

Inventor： Sivakumar Nagarajan

IPC: H01L29/40 ,  H01L23/48 ,  H01L21/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  C09J163/00 ,  C09J187/00 ,  C09J153/00

CPC classification number: H01L23/295 ,  C08L63/00 ,  C09J153/00 ,  C09J163/00 ,  C09J187/005 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/061 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/0645 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material.

Abstract translation: 本公开的实施方案涉及包括嵌段共聚物的底部填充材料。 在一个实施方案中，底部填充材料包括环氧材料和包含环氧亲水嵌段和环氧 - 疏水嵌段的共聚物，其中所述环氧亲水嵌段在环氧树脂材料中可混溶，环氧 - 疏水嵌段与环氧树脂共价键合 环氧疏水嵌段在环氧树脂材料中的微相区域中分离，并且环氧亲水嵌段被构造成限制环氧树脂材料的热膨胀或收缩。

公开(公告)号：US10115606B2

公开(公告)日：2018-10-30

申请号：US15139265

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Yuying Wei ,  Arjun Krishnan ,  Suriyakala Ramalingam ,  Yonghao Xiu ,  Beverly J. Canham ,  Sivakumar Nagarajan ,  Saikumar Jayaraman ,  Nisha Ananthakrishnan

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

公开(公告)号：US10475715B2

公开(公告)日：2019-11-12

申请号：US15037851

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Venmathy McMahan ,  Sivakumar Nagarajan ,  Elah Bozorg-Grayeli ,  Amrita Mallik ,  Kuang-Han Chu ,  Liwei Wang ,  Nisha Ananthakrishnan ,  Craig J. Weinman ,  Amram Eitan

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/18 ,  H01L23/373 ,  H01L25/065 ,  H01L25/07 ,  H01L23/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

公开(公告)号：US20240222274A1

公开(公告)日：2024-07-04

申请号：US18147820

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Sivakumar Nagarajan ,  Nisha Ananthakrishnan ,  Santosh Shaw ,  Wei Gao

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06541

Abstract: Integrated circuit (IC) dies, microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, an IC die may include a substrate, a front-end-of-line (FEOL) layer over the substrate, where the FEOL layer includes a plurality of transistors, a first back-end-of-line (BEOL) layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects.

公开(公告)号：US20210066265A1

公开(公告)日：2021-03-04

申请号：US16553544

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan ,  Sivakumar Nagarajan ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  William James Lambert

IPC: H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H03F3/213 ,  H01G2/06 ,  H01G2/10

Abstract: Disclosed herein are tunable capacitor arrangements in integrated circuit (IC) package substrates, as well as related methods and devices. For example, in some embodiments, an IC package substrate may include a first embedded capacitor, a second embedded capacitor, and a fuse electrically coupled between the first embedded capacitor and the second embedded capacitor such that when the fuse is in a closed state, the first embedded capacitor and the second embedded capacitor are connected in parallel, and when the fuse is in an open state, the first embedded capacitor and the second embedded capacitor are not connected in parallel.

公开(公告)号：US20160099190A1

公开(公告)日：2016-04-07

申请号：US14968716

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Sivakumar Nagarajan

IPC: H01L23/29 ,  H01L23/31 ,  C09J153/00 ,  C09J163/00 ,  C09J187/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/295 ,  C08L63/00 ,  C09J153/00 ,  C09J163/00 ,  C09J187/005 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/061 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/0645 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material.