公开(公告)号：US20230262281A1

公开(公告)日：2023-08-17

申请号：US18296264

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Aswin Padmanabhan ,  Satyeshwar Singh

IPC: H04N21/43

CPC classification number: H04N21/43076

Abstract: The present disclosure provides display network synchronization (sync) technologies and techniques using time-sensitive networking (TSN) and/or Precision Time Protocol (PTP) technologies. The display network sync mechanisms synchronize multiple display systems that are communicatively coupled together via a network. The display network sync mechanisms involve synchronizing the display systems with one another, synchronizing the various clocks and/or timers of each display system, monitoring clock drift of display clocks of individual display systems, and adjusting display signaling based on the monitored clock drift. The monitoring and adjusting of the display signaling can be accomplished without broadcasting the display signaling over the network connection.

公开(公告)号：US11360914B2

公开(公告)日：2022-06-14

申请号：US17008991

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10769078B2

公开(公告)日：2020-09-08

申请号：US16453995

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20230306552A1

公开(公告)日：2023-09-28

申请号：US17827305

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  David Puffer ,  Ankur Shah ,  Alan Previn Teres Alexis ,  Satyeshwar Singh

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/455

CPC classification number: G06T1/20 ,  G06F9/455 ,  G06T15/005

Abstract: Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.

公开(公告)号：US20240064202A1

公开(公告)日：2024-02-22

申请号：US18497839

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Aswin Padmanabhan ,  Satyeshwar Singh ,  Karthik Tyamgondlu ,  Marcos Paulo Da Silva

IPC: H04L67/1095 ,  G06F15/173 ,  H04L12/46

CPC classification number: H04L67/1095 ,  G06F15/17331 ,  H04L12/4645

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus to synchronize event data includes first circuitry to implement a user interface controller. The user interface controller of the example apparatus is to detect a user input, transmit a message including event data to a network interface controller (NIC), the event data corresponding to the user input, and provide the event data to a driver to cause an event corresponding to the event data to be rendered by the apparatus. The example apparatus also includes second circuitry to implement the NIC. The NIC of the example apparatus is to store the event data from the message in a local buffer of the NIC, obtain the event data from the local buffer using a direct memory access (DMA) request, and transmit a packet including the event data over a network.

公开(公告)号：US20220116678A1

公开(公告)日：2022-04-14

申请号：US17556497

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Karthik Tyamgondlu ,  Benjamin Thomas Cope ,  Satyeshwar Singh ,  Sangeeta Ghangam Manepalli ,  Aswin Padmanabhan

IPC: H04N21/43 ,  H03L7/08

Abstract: In one embodiment, video content displayed across a plurality of display devices is synchronized by first obtaining a first set of VSYNC timestamps for a display controller of a first video display device and a second set of VSYNC timestamps for a display controller of a second video display device. An adjustment factor is determined based on a comparison of the first and second VSYNC timestamps, and an adjusted VSYNC period for the display controller of the second video display device is programmed based on the determined adjustment factor. After a predetermined number of VSYNC cycles, the display controller of the second video display device reverts back to an original VSYNC period.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.