公开(公告)号：US11695051B2

公开(公告)日：2023-07-04

申请号：US16369517

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Ashish Penumatcha ,  Seung Hoon Sung ,  Scott Clendenning ,  Uygar Avci ,  Ian A. Young ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197643A1

公开(公告)日：2023-06-22

申请号：US17560062

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Sou-Chi Chang ,  Scott Clendenning ,  Matthew Metz

IPC: H01L23/64 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/642 ,  H01L21/0228 ,  H01L23/5286

Abstract: IC die and/or IC die packages including capacitors with a pyrochlore-based insulator material. The pyrochlore-based insulator material comprises a compound of a species A and a species B, each comprising one or more rare earths or metals. In the pyrochlore-based insulator material, oxygen content is advantageously more than three times and less than four times the amount of either of species A or B with crystalline pyrochlore phases having the composition A2B2O7. Within a capacitor, the pyrochlore-based insulator may be amorphous and/or may have one or more crystalline phases. The pyrochlore-based insulator has an exceedingly high relative permittivity of 50-100, or more. The pyrochlore-based insulator material may be deposited at low temperatures compatible with interconnect metallization processes practiced in IC die manufacture as well as IC die packaging.

公开(公告)号：US20240222482A1

公开(公告)日：2024-07-04

申请号：US18091192

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Rachel Steinhardt ,  Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Scott Clendenning ,  Tristan Tronic ,  Mahmut Sami Kavrik ,  Ande Kitamura

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a doping layer on metal chalcogenide nanoribbons outside of the channel region. The doping layer is a metal oxide that shifts the electrical characteristics of the nanoribbons and is formed by depositing a metal and oxidizing the metal by exposure to ozone and ultraviolet light.

公开(公告)号：US20240222441A1

公开(公告)日：2024-07-04

申请号：US18091197

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Carl Naylor ,  Chelsey Dorow ,  Chia-Ching Lin ,  Dominique Adams ,  Kevin O'Brien ,  Matthew Metz ,  Scott Clendenning ,  Sudarat Lee ,  Tristan Tronic ,  Uygar Avci

IPC: H01L29/40 ,  H01L21/04 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/44 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/043 ,  H01L21/044 ,  H01L21/28264 ,  H01L21/32136 ,  H01L21/44 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/454 ,  H01L29/78648 ,  H01L29/4908

Abstract: Devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2D materials for transistor devices. A transistor structure includes a gate dielectric structure on a 2D semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2D semiconductor material layer. The source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.

公开(公告)号：US20250112155A1

公开(公告)日：2025-04-03

申请号：US18374532

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Scott Clendenning ,  Feras Eid ,  Robert Jordan ,  Wenhao Li ,  Jiun-Ruey Chen ,  Tayseer Mahdi ,  Carlos Felipe Bedoya Arroyave ,  Shashi Bhushan Sinha ,  Anandi Roy ,  Tristan Tronic ,  Dominique Adams ,  William Brezinski ,  Richard Vreeland ,  Thomas Sounart ,  Brian Barley ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.

公开(公告)号：US20220415818A1

公开(公告)日：2022-12-29

申请号：US17358962

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Jasmeet Chawla ,  Matthew Metz ,  Sean King ,  Ramanan Chebiam ,  Mauro Kobrinsky ,  Scott Clendenning ,  Sudarat Lee ,  Christopher Jezewski ,  Sunny Chugh ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768

Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.