公开(公告)号：US20210035886A1

公开(公告)日：2021-02-04

申请号：US16529639

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US11004768B2

公开(公告)日：2021-05-11

申请号：US16529639

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US11881438B2

公开(公告)日：2024-01-23

申请号：US16746732

申请日：2020-01-17

Applicant: Intel Corporation

Inventor： Elah Bozorg-Grayeli ,  Kyle Arrington ,  Sergio Chan Arguedas ,  Aravindha Antoniswamy

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/16 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3733 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/16 ,  H01L23/367 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/3511

Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.

公开(公告)号：US11776864B2

公开(公告)日：2023-10-03

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Edvin Cetegen ,  Nicholas Neal ,  Sergio Chan Arguedas

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/10152 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US11328978B2

公开(公告)日：2022-05-10

申请号：US16639545

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna M. Swan ,  Sergio Chan Arguedas ,  John J. Beatty

IPC: H01L23/367 ,  H01L21/48 ,  H01L49/02 ,  H01L23/00 ,  H01L23/10

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

公开(公告)号：US11776869B2

公开(公告)日：2023-10-03

申请号：US17718031

申请日：2022-04-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna M. Swan ,  Sergio Chan Arguedas ,  John J. Beatty

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/10 ,  H01L49/02 ,  H01L23/42

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L28/40 ,  H01L23/10 ,  H01L23/42 ,  H01L24/30 ,  H01L24/32

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

公开(公告)号：US11328979B2

公开(公告)日：2022-05-10

申请号：US16639956

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Dinesh Padmanabhan Ramalekshmi Thanu ,  Sergio Chan Arguedas ,  Johanna M. Swan ,  John J. Beatty

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.

公开(公告)号：US20210225729A1

公开(公告)日：2021-07-22

申请号：US16746732

申请日：2020-01-17

Applicant: Intel Corporation

Inventor： Elah Bozorg-Grayeli ,  Kyle Arrington ,  Sergio Chan Arguedas ,  Aravindha Antoniswamy

IPC: H01L23/373 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48

Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.