公开(公告)号：US11088103B2

公开(公告)日：2021-08-10

申请号：US16646084

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Xiaoying Guo ,  Aleksandar Aleksov ,  Steve S. Cho ,  Leonel Arana ,  Robert May ,  Gang Duan

IPC: H01L23/52 ,  H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US10297563B2

公开(公告)日：2019-05-21

申请号：US15267065

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Amanda E. Schuckman ,  Steve S. Cho

IPC: H01L23/00

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20240194548A1

公开(公告)日：2024-06-13

申请号：US18065250

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Steve S. Cho ,  Hiroki Tanaka ,  Haobo Chen ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/15 ,  C23C18/16 ,  C23C18/18 ,  C23C18/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/15 ,  C23C18/1639 ,  C23C18/165 ,  C23C18/1855 ,  C23C18/48 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1011 ,  H01L2924/1511 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Apparatus and methods for electroless surface finishing on glass. A planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. Planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. The planar surface enables finishing the substrate surface with an electroless NiPdAu process.

公开(公告)号：US11776864B2

公开(公告)日：2023-10-03

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Edvin Cetegen ,  Nicholas Neal ,  Sergio Chan Arguedas

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/10152 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US12068172B2

公开(公告)日：2024-08-20

申请号：US16525985

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Wei-Lun K. Jen ,  Steve S. Cho ,  Jason M. Gamba ,  Javier Soto Gonzalez

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L21/4846 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

公开(公告)号：US20180076161A1

公开(公告)日：2018-03-15

申请号：US15267065

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Amanda E. Schuckman ,  Steve S. Cho

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16157 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.