公开(公告)号：US20220130721A1

公开(公告)日：2022-04-28

申请号：US17076870

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Shashi Vyas ,  Akm Shaestagir Chowdhury ,  Andy Chih-Hung Wei ,  Charles Henry Wallace

IPC: H01L21/768 ,  H01L23/522

Abstract: Methods for fabricating an IC structure by applying self-assembled monolayers (SAMs) are disclosed. An example IC structure includes a stack of three metallization layers provided over a support structure, where the first metallization layer includes a bottom metal line, the third metallization layer includes a top metal line, and the second metallization layer includes a via coupled between the bottom metal line and the top metal line, where via's sidewalls are enclosed by a first dielectric material. Application of one or more SAMs results in at least a portion of the via's sidewalls being lined with a second dielectric material so that the second dielectric material is between the first dielectric material and an electrically conductive material of the via, where the dielectric constant of the second dielectric material is higher than that of the first dielectric material and lower than about 6.

公开(公告)号：US20230299040A1

公开(公告)日：2023-09-21

申请号：US17699024

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Jay Prakash Gupta ,  Souvik Ghosh ,  Kimin Jun ,  Bhupendra Kumar ,  Shashi Vyas ,  Anup Pancholi

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03849 ,  H01L2224/08147 ,  H01L2224/05687 ,  H01L2224/05147 ,  H01L2224/05666 ,  H01L2224/05187 ,  H01L2224/8009 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80948 ,  H01L2924/35121

Abstract: A microelectronic assembly and a method of forming same. The assembly includes: first and second microelectronic structures; and an interface layer between the two microelectronic structures including dielectric portions in registration with dielectric layers of each of the microelectronic structures, and electrically conductive portions in registration with electrically conductive structures of each of the microelectronic structures, wherein the dielectric portions include an oxide of a metal, and the electrically conductive portions include the metal.

公开(公告)号：US12249577B2

公开(公告)日：2025-03-11

申请号：US17125680

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Shashi Vyas ,  Sudipto Naskar ,  Charles Wallace

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures, a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, the cap structure includes a top surface and a sidewall surface and a liner comprising a third dielectric on the top surface and on the sidewall surface.

公开(公告)号：US20220199544A1

公开(公告)日：2022-06-23

申请号：US17125680

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Shashi Vyas ,  Sudipto Naskar ,  Charles Wallace

IPC: H01L23/532 ,  H01L21/768

Abstract: An integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures, a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, the cap structure includes a top surface and a sidewall surface and a liner comprising a third dielectric on the top surface and on the sidewall surface.