公开(公告)号：US11769753B2

公开(公告)日：2023-09-26

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George Vakanas ,  Aastha Uppal ,  Shereen Elhalawaty ,  Aaron McCann ,  Edvin Cetegen ,  Tannaz Harirchian ,  Saikumar Jayaraman

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/49 ,  H10B12/00

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.