公开(公告)号：US09934143B2

公开(公告)日：2018-04-03

申请号：US14038659

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Suneeta Sah ,  John H. Crawford ,  Brian S. Morris

IPC: G06F13/12 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0292 ,  G06F12/0638

Abstract: A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

公开(公告)号：US09910604B2

公开(公告)日：2018-03-06

申请号：US15011591

申请日：2016-01-31

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Suneeta Sah

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G06F3/0613 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/4076

Abstract: Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170024148A1

公开(公告)日：2017-01-26

申请号：US15011591

申请日：2016-01-31

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Suneeta Sah

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0613 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/4076

Abstract: Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了管理存储器刷新操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和存储器控制器逻辑，用于确定存储器系统的存储器刷新频率，并且根据存储器刷新频率向连接到存储器控制器的至少一个存储器组中的刷新控制逻辑发送刷新命令 。 还公开并要求保护其他实施例。

公开(公告)号：US09269436B2

公开(公告)日：2016-02-23

申请号：US14133011

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Abstract translation: 公开了用于基于侵入者行的逻辑地址和与易失性存储器相关联的地址转换方案来确定易失性存储器的一个或多个受害行的逻辑地址的示例。 其他的例子被描述和要求保护。

公开(公告)号：US10146711B2

公开(公告)日：2018-12-04

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US09269417B2

公开(公告)日：2016-02-23

申请号：US13761385

申请日：2013-02-07

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Suneeta Sah

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G06F3/0613 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/4076

Abstract: Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了管理存储器刷新操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和存储器控制器逻辑，用于确定存储器系统的存储器刷新频率，并且根据存储器刷新频率向连接到存储器控制器的至少一个存储器组中的刷新控制逻辑发送刷新命令 。 还公开并要求保护其他实施例。

公开(公告)号：US09824754B2

公开(公告)日：2017-11-21

申请号：US15000643

申请日：2016-01-19

Applicant: INTEL CORPORATION

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

公开(公告)号：US09436632B2

公开(公告)日：2016-09-06

申请号：US14560976

申请日：2014-12-04

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Klaus J. Ruff ,  George Vergis ,  Suneeta Sah

IPC: G06F13/28 ,  G06F11/10 ,  G06F11/16 ,  G11C29/44 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

公开(公告)号：US10592445B2

公开(公告)日：2020-03-17

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox ,  Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F11/16 ,  G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00 ,  G11C5/04 ,  G11C7/10

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20170199830A1

公开(公告)日：2017-07-13

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.