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公开(公告)号：US09405358B2
公开(公告)日：2016-08-02
申请号：US14515694
申请日：2014-10-16
Applicant: Intel Corporation
Inventor： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3237 , G06F1/324 , Y02D10/128 , Y02D50/20
Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
Abstract translation: 在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。 当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。
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2.发明申请APPARATUS AND METHOD TO PROVIDE A THERMAL PARAMETER REPORT FOR A MULTI-CHIP PACKAGE 审中-公开提供多芯片封装的热参数报告的装置和方法公开(公告)号：US20160179158A1
公开(公告)日：2016-06-23
申请号：US14852859
申请日：2015-09-14
Applicant: Intel Corporation
Inventor： Tessil Thomas , Robin A. Steinbrecher , Sandeep Ahuja , Michael Berktold , Timothy Y. Kam , Howard Chin , Phani Kumar Kandula , Krishnakanth V. Sistla
CPC classification number: G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F3/0412 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括至少一个核心和电源管理逻辑。 电源管理逻辑用于从包括处理器的封装内的多个管芯接收温度数据，并且确定多个温度控制裕度的最小温度控制裕度。 每个温度控制余量将基于与管芯相关联的相应的热控制温度并且还基于与管芯相关联的相应的温度数据来确定。 电源管理逻辑还可以生成包含最小温度控制余量的热报告，并存储热报告。 描述和要求保护其他实施例。
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公开(公告)号：US20160077567A1
公开(公告)日：2016-03-17
申请号：US14948174
申请日：2015-11-20
Applicant: Intel Corporation
Inventor： Gururaj K. Shamanna , Stefan Rusu , Phani Kumar Kandula , Sankalan Prasad , Mandar R. Ranade , Narayanan Natarajan , Tessil Thomas
CPC classification number: G06F1/28 , G05F1/625 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。
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公开(公告)号：US10691626B2
公开(公告)日：2020-06-23
申请号：US16405524
申请日：2019-05-07
Applicant: Intel Corporation
Inventor： Bill Nale , Raj K. Ramanujan , Muthukumar P. Swaminathan , Tessil Thomas , Taarinya Polepeddi
IPC: G06F13/16 , G06F13/40 , G06F13/42 , G06F12/0804 , G06F9/46 , G06F12/0868 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0897 , G06F12/0811
Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
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公开(公告)号：US10241943B2
公开(公告)日：2019-03-26
申请号：US15857992
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Bill Nale , Raj K. Ramanujan , Muthukumar P. Swaminathan , Tessil Thomas , Taarinya Polepeddi
IPC: G06F13/16 , G06F13/42 , G06F12/0868 , G06F11/10 , G06F12/0802 , G06F12/0804 , G06F12/0897 , G06F9/46 , G06F13/40 , G06F12/02 , G06F12/0811
Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol
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Patent Agency Ranking
公开(公告)号：US10048744B2
公开(公告)日：2018-08-14
申请号：US14554384
申请日：2014-11-26
Applicant: Intel Corporation
Inventor： Tessil Thomas , Phani Kumar Kandula , Ramamurthy Krithivas , Howard Chin , Ian M. Steiner , Vivek Garg
Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
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公开(公告)号：US09921630B2
公开(公告)日：2018-03-20
申请号：US14948174
申请日：2015-11-20
Applicant: Intel Corporation
Inventor： Gururaj K. Shamanna , Stefan Rusu , Phani Kumar Kandula , Sankalan Prasad , Mandar R. Ranade , Narayanan Natarajan , Tessil Thomas
CPC classification number: G06F1/28 , G05F1/625 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
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公开(公告)号：US11841752B2
公开(公告)日：2023-12-12
申请号：US17338547
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Tessil Thomas , Lokesh Sharma , Buck Gremel , Ian Steiner
IPC: G06F1/20 , G06F1/3234
CPC classification number: G06F1/206 , G06F1/3243 , Y02D10/00
Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.
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公开(公告)号：US20200301490A1
公开(公告)日：2020-09-24
申请号：US16898603
申请日：2020-06-11
Applicant: Intel Corporation
Inventor： Tessil Thomas , Robin A. Steinbrecher , Sandeep Ahuja , Michael Berktold , Timothy Y. Kam , Howard Chin , Phani Kumar Kandula , Krishnakanth V. Sistla
IPC: G06F1/20 , G06F1/3296 , G06F1/3206 , G06F1/324 , G06F3/041
Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
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公开(公告)号：US20180335831A1
公开(公告)日：2018-11-22
申请号：US16052375
申请日：2018-08-01
Applicant: Intel Corporation
Inventor： Tessil Thomas , Phani Kumar Kandula , Ramamurthy Krithivas , Howard Chin , Ian M. Steiner , Vivek Garg
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/32 , G06F1/3206 , G06F1/324 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
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