公开(公告)号：US20210232426A1

公开(公告)日：2021-07-29

申请号：US17094412

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ian Steiner ,  Leeor Peled ,  Michael Prinke ,  Eylon Toledano

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

公开(公告)号：US11841752B2

公开(公告)日：2023-12-12

申请号：US17338547

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Lokesh Sharma ,  Buck Gremel ,  Ian Steiner

IPC: G06F1/20 ,  G06F1/3234

CPC classification number: G06F1/206 ,  G06F1/3243 ,  Y02D10/00

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

公开(公告)号：US11079819B2

公开(公告)日：2021-08-03

申请号：US16215978

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Lokesh Sharma ,  Buck Gremel ,  Ian Steiner

IPC: G06F1/3234 ,  G06F1/20

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

公开(公告)号：US20200310865A1

公开(公告)日：2020-10-01

申请号：US16370248

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ian Steiner ,  Leeor Peled ,  Michael Prinke ,  Eylon Toledano

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

公开(公告)号：US09377841B2

公开(公告)日：2016-06-28

申请号：US13889785

申请日：2013-05-08

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Ian Steiner ,  Avinash Ananthakrishnan ,  Krishnakanth Sistla ,  Chris Poirier ,  Matthew Bace ,  Eric Dehaemer

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元以控制处理器的功率消耗，其中功率控制单元包括控制逻辑以减少最大操作 如果在第一时间段内发生第一数量的强制执行状态转换或在第二时间段内发生第二数量的强制执行状态转换，则处理器的频率。 描述和要求保护其他实施例。

公开(公告)号：US20220413720A1

公开(公告)日：2022-12-29

申请号：US17359334

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ian Steiner ,  Vasudevan Srinivasan ,  Ankush Varma ,  Nikhil Gupta ,  Stanley Chen

IPC: G06F3/06

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

公开(公告)号：US20210294400A1

公开(公告)日：2021-09-23

申请号：US17338547

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Lokesh Sharma ,  Buck Gremel ,  Ian Steiner

IPC: G06F1/20 ,  G06F1/3234

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

公开(公告)号：US20190107872A1

公开(公告)日：2019-04-11

申请号：US16215978

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Lokesh Sharma ,  Buck Gremel ,  Ian Steiner

IPC: G06F1/20 ,  G06F1/3234

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.