公开(公告)号：US20240355915A1

公开(公告)日：2024-10-24

申请号：US18137731

申请日：2023-04-21

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Clifford J. Engel ,  Debaleena Nandi ,  Gary Allen ,  Nicholas A. Thomson ,  Saurabh Acharya ,  Umang Desai ,  Vivek Vishwakarma ,  Charles H. Wallace

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.