公开(公告)号：US20230193473A1

公开(公告)日：2023-06-22

申请号：US17559897

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Debaleena Nandi ,  Gilbert Dewey ,  Tahir Ghani ,  Nazila Haratipour ,  Mauro J. Kobrinsky ,  Anand Murthy

IPC: C23C28/00 ,  H01L23/538

CPC classification number: C23C28/34 ,  C23C28/32 ,  C23C28/36 ,  H01L23/5383

Abstract: The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.

公开(公告)号：US20220416032A1

公开(公告)日：2022-12-29

申请号：US17358436

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena Nandi ,  Chi-Hing Choi ,  Gilbert Dewey ,  Harold Kennel ,  Omair Saadat ,  Jitendra Kumar Jha ,  Adedapo Oni ,  Nazila Haratipour ,  Anand Murthy ,  Tahir Ghani

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/768

Abstract: Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

公开(公告)号：US20250006806A1

公开(公告)日：2025-01-02

申请号：US18346087

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Alexander Badmaev ,  Zhiyi Chen ,  Debaleena Nandi ,  Tahir Ghani

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.

公开(公告)号：US20240355915A1

公开(公告)日：2024-10-24

申请号：US18137731

申请日：2023-04-21

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Clifford J. Engel ,  Debaleena Nandi ,  Gary Allen ,  Nicholas A. Thomson ,  Saurabh Acharya ,  Umang Desai ,  Vivek Vishwakarma ,  Charles H. Wallace

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.