公开(公告)号：US10652353B2

公开(公告)日：2020-05-12

申请号：US14864369

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Venkata Krishnan ,  Srinivas Sridharan ,  David A. Webb

IPC: G06F15/16 ,  H04L29/08 ,  G06F15/173

Abstract: Technologies for communication with direct data placement include a number of computing nodes in communication over a network. Each computing node includes a many-core processor having an integrated host fabric interface (HFI) that maintains an association table (AT). In response to receiving a message from a remote device, the HFI determines whether the AT includes an entry associating one or more parameters of the message to a destination processor core. If so, the HFI causes a data transfer agent (DTA) of the destination core to receive the message data. The DTA may place the message data in a private cache of the destination core. Message parameters may include a destination process identifier or other network address and a virtual memory address range. The HFI may automatically update the AT based on communication operations generated by software executed by the processor cores. Other embodiments are described and claimed.

公开(公告)号：US11327894B2

公开(公告)日：2022-05-10

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20190004958A1

公开(公告)日：2019-01-03

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20170094010A1

公开(公告)日：2017-03-30

申请号：US14864369

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Venkata Krishnan ,  Srinivas Sridharan ,  David A. Webb

IPC: H04L29/08 ,  G06F9/455 ,  H04L12/24

CPC classification number: H04L67/2852 ,  G06F9/46

Abstract: Technologies for communication with direct data placement include a number of computing nodes in communication over a network. Each computing node includes a many-core processor having an integrated host fabric interface (HFI) that maintains an association table (AT). In response to receiving a message from a remote device, the HFI determines whether the AT includes an entry associating one or more parameters of the message to a destination processor core. If so, the HFI causes a data transfer agent (DTA) of the destination core to receive the message data. The DTA may place the message data in a private cache of the destination core. Message parameters may include a destination process identifier or other network address and a virtual memory address range. The HFI may automatically update the AT based on communication operations generated by software executed by the processor cores. Other embodiments are described and claimed.

公开(公告)号：US10606755B2

公开(公告)日：2020-03-31

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10073775B2

公开(公告)日：2018-09-11

申请号：US15089035

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Christopher B. Wilerkson ,  Ren Wang ,  Antoine Kaufmann ,  Anil Vasudevan ,  Robert G. Blankenship ,  Venkata Krishnan ,  Tsung-Yuan C. Tai

IPC: G06F12/00 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/0862 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.

公开(公告)号：US11816036B2

公开(公告)日：2023-11-14

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

CPC classification number: G06F12/0868 ,  G06F3/065 ,  G06F3/068 ,  G06F3/0619 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/311 ,  G06F2212/6046

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20220261351A1

公开(公告)日：2022-08-18

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20210049102A1

公开(公告)日：2021-02-18

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20190303303A1

公开(公告)日：2019-10-03

申请号：US15940719

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Venkata Krishnan ,  Lawrence Stewart ,  Anil Vasudevan ,  Ren Wang

IPC: G06F12/123 ,  G06F12/122 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0811

Abstract: A method for detecting repetitive data accesses and automatically storing the data into the local cache, the method including: storing a cache line in a first cache of a first processor; tracking accesses to the cache line by monitoring executions of a snapshot instruction made by a second processor; and controlling enablement of a load operation based on the tracked accesses. The load operation is performed by storing a copy of the cache line into a local cache of the second processor and changing the cache coherence state of the cache line in the first cache to a shared state.