公开(公告)号：US09910475B2

公开(公告)日：2018-03-06

申请号：US14580553

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F1/3206 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/348 ,  G06F2201/86

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US10656697B2

公开(公告)日：2020-05-19

申请号：US15911577

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3206

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US20190050041A1

公开(公告)日：2019-02-14

申请号：US15911577

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.