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公开(公告)号：US09910475B2
公开(公告)日：2018-03-06
申请号：US14580553
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
CPC classification number: G06F1/3206 , G06F11/3024 , G06F11/3055 , G06F11/348 , G06F2201/86
Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
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公开(公告)号：US09696997B2
公开(公告)日：2017-07-04
申请号：US14992658
申请日：2016-01-11
Applicant: INTEL CORPORATION
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
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Patent Agency Ranking
公开(公告)号：US09612938B2
公开(公告)日：2017-04-04
申请号：US13895595
申请日：2013-05-16
Applicant: Intel Corporation
Inventor： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , Md A. Rahman
CPC classification number: G06F11/3636 , G06F11/3024 , G06F11/3055 , G06F11/3476 , G06F11/348 , G06F2201/865
Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
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公开(公告)号：US20160117171A1
公开(公告)日：2016-04-28
申请号：US14992658
申请日：2016-01-11
Applicant: INTEL CORPORATION
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。
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公开(公告)号：US10656697B2
公开(公告)日：2020-05-19
申请号：US15911577
申请日：2018-03-05
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
IPC: G06F1/32 , G06F11/34 , G06F11/30 , G06F1/3206
Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
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公开(公告)号：US20190050041A1
公开(公告)日：2019-02-14
申请号：US15911577
申请日：2018-03-05
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
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公开(公告)号：US09262163B2
公开(公告)日：2016-02-16
申请号：US13730834
申请日：2012-12-29
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。
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