公开(公告)号：US09202056B2

公开(公告)日：2015-12-01

申请号：US13839048

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： William C. Rash ,  Martin G. Dixon ,  Yazmin A. Santiago

IPC: G06F11/00 ,  G06F21/57 ,  G06F12/14 ,  G06F7/04

CPC classification number: G06F21/57

Abstract: Embodiments of an invention for inter-processor attestation hardware are disclosed. In one embodiment, an apparatus includes first attestation hardware associated with a first portion of a system. The first attestation hardware is to attest to a second portion of the system that the first portion of the system is secure.

Abstract translation: 公开了用于处理器间认证硬件的发明的实施例。 在一个实施例中，装置包括与系统的第一部分相关联的第一认证硬件。 第一个认证硬件是证明系统的第一部分是系统的第二部分是安全的。

公开(公告)号：US20160216967A1

公开(公告)日：2016-07-28

申请号：US15089883

申请日：2016-04-04

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  William C. Rash ,  Yazmin A. Santiago

IPC: G06F9/30 ,  G11C7/10 ,  G06F12/14

CPC classification number: G06F9/30087 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/6028 ,  G11C7/1072 ,  Y02D10/13

Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.

Abstract translation: 一个方面的处理器包括多个逻辑处理器。 多个的第一逻辑处理器是执行包括存储器访问同步指令的软件，所述存储器访问同步指令旨在同步对存储器的访问。 处理器还包括存储器访问同步放宽逻辑，当处理器处于松弛的存储器访问同步模式时，该存储器访问同步放松逻辑防止存储器访问同步指令同步对存储器的访问。

公开(公告)号：US09323535B2

公开(公告)日：2016-04-26

申请号：US13931544

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Martin Guy Dixon ,  William C. Rash ,  Yazmin A. Santiago

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3855 ,  G06F9/3891

Abstract: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction. The activation instruction is to occur before the enforcement instruction in a program order. The processor also includes an instruction order enforcement module. The instruction order enforcement module, in response to the pair of the instruction order enforcement instructions, is to prevent instructions occurring after the enforcement instruction in the program order, from being processed prior to the activation instruction, in an out-of-order portion of the processor. Other processors are also disclosed, as are various methods, systems, and instructions.

Abstract translation: 一个方面的处理器包括一个指令提取单元来获取一对指令执行指令。 该指令执行指令对是处理器指令集的一部分。 一对指令执行指令包括激活指令和执行指令。 激活指令是在程序命令执行指令之前发生的。 处理器还包括指令执行模块。 指令指令执行模块响应于该指令执行指令对，是为了防止在程序命令执行指令之后发生的指令在激活指令之前被处理在无效部分 处理器。 还公开了其他处理器，以及各种方法，系统和指令。

公开(公告)号：US09304940B2

公开(公告)日：2016-04-05

申请号：US13844729

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  William C. Rash ,  Yazmin A. Santiago

IPC: G06F12/14 ,  G06F12/08

CPC classification number: G06F9/30087 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/6028 ,  G11C7/1072 ,  Y02D10/13

Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.

Abstract translation: 一个方面的处理器包括多个逻辑处理器。 多个的第一逻辑处理器是执行包括存储器访问同步指令的软件，所述存储器访问同步指令旨在同步对存储器的访问。 处理器还包括存储器访问同步放宽逻辑，当处理器处于松弛的存储器访问同步模式时，该存储器访问同步放松逻辑防止存储器访问同步指令同步对存储器的访问。

公开(公告)号：US20150006851A1

公开(公告)日：2015-01-01

申请号：US13931544

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Martin Guy Dixon ,  William C. Rash ,  Yazmin A. Santiago

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3855 ,  G06F9/3891

Abstract: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction. The activation instruction is to occur before the enforcement instruction in a program order. The processor also includes an instruction order enforcement module. The instruction order enforcement module, in response to the pair of the instruction order enforcement instructions, is to prevent instructions occurring after the enforcement instruction in the program order, from being processed prior to the activation instruction, in an out-of-order portion of the processor. Other processors are also disclosed, as are various methods, systems, and instructions.

Abstract translation: 一个方面的处理器包括一个指令提取单元来获取一对指令执行指令。 该指令执行指令对是处理器指令集的一部分。 一对指令执行指令包括激活指令和执行指令。 激活指令是在程序命令执行指令之前发生的。 处理器还包括指令执行模块。 指令指令执行模块响应于该指令执行指令对，是为了防止在程序命令执行指令之后发生的指令在激活指令之前被处理在无效部分 处理器。 还公开了其他处理器，以及各种方法，系统和指令。

公开(公告)号：US10235175B2

公开(公告)日：2019-03-19

申请号：US15089883

申请日：2016-04-04

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  William C. Rash ,  Yazmin A. Santiago

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/14 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0862 ,  G11C7/10

Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.

公开(公告)号：US09703562B2

公开(公告)日：2017-07-11

申请号：US13844881

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： William C. Rash ,  Bret L. Toll ,  Scott D. Hahn ,  Glenn J. Hinton

IPC: G06F9/30 ,  G06F9/40

CPC classification number: G06F9/30145 ,  G06F9/3017 ,  G06F9/30189

Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.

公开(公告)号：US10073513B2

公开(公告)日：2018-09-11

申请号：US15133688

申请日：2016-04-20

Applicant: Intel Corporation

Inventor： William C. Rash ,  Martin G. Dixon ,  Yazmin A. Santiago

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.

公开(公告)号：US09395990B2

公开(公告)日：2016-07-19

申请号：US13931070

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： William C. Rash ,  Yazmin A. Santiago ,  Martin Guy Dixon

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30043 ,  G06F9/30189 ,  G06F9/3836

Abstract: A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates a memory location of a memory as a source operand and indicates a register as a destination operand. The method includes loading data from the indicated memory location to the processor in response to the partial width load instruction. The method includes writing at least a portion of the loaded data to a partial width of the register in response to the partial width load instruction. The method includes finishing writing the register with a set of bits stored in a remaining width of the register that have bit values that depend on a partial width load mode of the processor. The partial width load instruction does not indicate the partial width load mode. Other methods, processors, and systems are also disclosed.

Abstract translation: 一种方面的方法由处理器执行。 该方法包括接收部分宽度加载指令。 部分宽度加载指令表示作为源操作数的存储器的存储器位置，并且将寄存器指示为目的地操作数。 该方法包括响应于部分宽度加载指令将数据从指示的存储器位置加载到处理器。 该方法包括响应于部分宽度加载指令将加载的数据的至少一部分写入寄存器的部分宽度。 该方法包括用存储在寄存器的剩余宽度中的一组位来完成对寄存器的写入，这些位具有取决于处理器的部分宽度负载模式的位值。 部分宽度加载指令不表示部分宽度加载模式。 还公开了其它方法，处理器和系统。

公开(公告)号：US09354681B2

公开(公告)日：2016-05-31

申请号：US13930044

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： William C. Rash ,  Martin G. Dixon ,  Yazmin A. Santiago

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3246 ,  G06F1/3275 ,  G06F9/30083 ,  G06F9/30101 ,  G06F9/30189

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核。 每个核心包括用于检测一个或多个电力管理事件的核心电力单元，并且响应于一个或多个电力管理事件，在核心中发起受保护的电力管理模式。 在受保护的电源管理模式下，可能会禁用到核心的软件中断。 核心是在受保护的电源管理模式下执行电源管理代码。 描述和要求保护其他实施例。