公开(公告)号：US20240176941A1

公开(公告)日：2024-05-30

申请号：US18552213

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Jorge A. Alvarez ,  Jose de Jesus Jauregui Ruelas ,  Vijaya K. Kunda ,  Hong-Yi Luoh ,  Yanwu Wang ,  Chunfei Ye

IPC: G06F30/3953 ,  G06F30/392 ,  G06F30/398 ,  G06F119/10

CPC classification number: G06F30/3953 ,  G06F30/392 ,  G06F30/398 ,  G06F2119/10

Abstract: Signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. The widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. The signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. The edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. The edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.