公开(公告)号：US09104223B2

公开(公告)日：2015-08-11

申请号：US13894275

申请日：2013-05-14

Applicant: Intel IP Corporation

Inventor： Kai Zhong ,  Chuanzhao Yu

IPC: G05F1/575 ,  G05F1/59 ,  G05F1/46 ,  G05F3/08

CPC classification number: G05F1/575 ,  G05F1/462 ,  G05F1/59 ,  G05F3/08

Abstract: A method of reducing voltage variations in a power supply may include generating an intermediate voltage and setting a first-transistor gate voltage at a first-transistor gate of a first transistor of the power supply based on the intermediate voltage. The method may also include setting an output voltage at an output node of the power supply based on a second-transistor gate voltage at a second-transistor gate of a second transistor. Additionally, the method may include setting the second-transistor gate voltage based on the first-transistor gate voltage such that the output voltage is based on the intermediate voltage, a first-transistor threshold voltage of the first transistor, and a second-transistor threshold voltage of the second transistor and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out.

Abstract translation: 一种降低电源中的电压变化的方法可以包括产生中间电压并且基于中间电压在电源的第一晶体管的第一晶体管栅极处设置第一晶体管栅极电压。 该方法还可以包括基于第二晶体管的第二晶体管栅极处的第二晶体管栅极电压来设置电源的输出节点处的输出电压。 另外，该方法可以包括基于第一晶体管栅极电压设置第二晶体管栅极电压，使得输出电压基于中间电压，第一晶体管的第一晶体管阈值电压和第二晶体管阈值 并且使得第一晶体管阈值电压和第二晶体管阈值电压的变化至少部分地相互抵消。