-
公开(公告)号：US11437971B2
公开(公告)日：2022-09-06
申请号：US16976084
申请日：2018-06-27
Applicant: Intel IP Corporation
Inventor： Chuanzhao Yu , Maximilian Eschbaumer
Abstract: Embodiments relate to a transformer-based impedance matching network that may dynamically change its characteristic impedance by engaging different inductor branches on a primary side and optionally, on the secondary side. A primary side transformer circuit includes a primary inductor (311) and secondary inductor (321) configured to provide impedance matching over a first frequency band. One or more additional inductor branches (314A, 314B, are switchably coupled to either or both of the primary and secondary inductors to modify the impedance matching characteristics over additional operating frequencies. One or more LC filter branches (321, 322, 326, 327, 336, 330) can be included at the output of the secondary side to filter harmonic frequencies in each of the operating frequency bands.
-
Patent Agency Ranking
公开(公告)号：US20210065963A1
公开(公告)日：2021-03-04
申请号：US16958049
申请日：2018-03-30
Applicant: Intel IP Corporation
Inventor： Chuanzhao Yu , Qiang Li , David Newman
Abstract: A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. The second layer element includes side by side first and second wire components in parallel spaced relation extending around the center axis and the first wire component is connected to the first layer wire element to form a primary turn winding. A third layer includes a third layer wire element extending around the center axis and connected to the second wire component of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.
-
公开(公告)号：US09337874B1
公开(公告)日：2016-05-10
申请号：US14575939
申请日：2014-12-18
Applicant: Intel IP Corporation
Inventor： Chuanzhao Yu , Mark Kirschenmann
Abstract: Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment, input binary bits are divided into two sets of bits, where one set is provided to a binary to thermometer coder to generate an output mixed with a clock signal to operatively provide a reverse order inverted bit pattern. The other set of binary bits is subject to exclusive-or processing such that processing of the two sets operatively provides a mixed hybrid code to be fed from high speed digital signal processor. Additional apparatus, systems, and methods are disclosed.
Abstract translation: 提供高速数字信号处理器的装置和方法可以在基本上所有的数字发射机设计中实现。 在一个实施例中，输入二进制位被分成两组位，其中一组被提供给二进制到温度计编码器，以产生与时钟信号混合的输出，以可操作地提供反向反转位模式。 另一组二进制位被进行独占或处理，使得两组的处理可操作地提供要从高速数字信号处理器馈送的混合混合码。 公开了附加装置，系统和方法。
-
公开(公告)号：US20200321956A1
公开(公告)日：2020-10-08
申请号：US16766843
申请日：2018-03-28
Applicant: Intel IP Corporation
Inventor： Chuanzhao Yu , Stepha Leuschner , David Newman
Abstract: Techniques are provided for fanning out a signal from a balun. In various aspects, the system can include a balun configured to receive a signal for transmission at an input and to provide a representation of the signal at an output, a plurality of pass gate circuits, each pass gate circuit configured to receive the representation of the signal at a first node, to receive a control signal at a second node to pass the representation of the signal to a third node when the control signal is in a first state, and to isolate the representation of the signal from the third node when the control signal is in a second state. The first state of the control signal can include a non-zero voltage, and the second state of the control signal can include the non-zero voltage with a polarity opposite the non-zero voltage of the first state.
-
公开(公告)号：US09104223B2
公开(公告)日：2015-08-11
申请号：US13894275
申请日：2013-05-14
Applicant: Intel IP Corporation
Inventor： Kai Zhong , Chuanzhao Yu
Abstract: A method of reducing voltage variations in a power supply may include generating an intermediate voltage and setting a first-transistor gate voltage at a first-transistor gate of a first transistor of the power supply based on the intermediate voltage. The method may also include setting an output voltage at an output node of the power supply based on a second-transistor gate voltage at a second-transistor gate of a second transistor. Additionally, the method may include setting the second-transistor gate voltage based on the first-transistor gate voltage such that the output voltage is based on the intermediate voltage, a first-transistor threshold voltage of the first transistor, and a second-transistor threshold voltage of the second transistor and such that variations in the first-transistor threshold voltage and the second-transistor threshold voltage at least partially cancel each other out.
Abstract translation: 一种降低电源中的电压变化的方法可以包括产生中间电压并且基于中间电压在电源的第一晶体管的第一晶体管栅极处设置第一晶体管栅极电压。 该方法还可以包括基于第二晶体管的第二晶体管栅极处的第二晶体管栅极电压来设置电源的输出节点处的输出电压。 另外，该方法可以包括基于第一晶体管栅极电压设置第二晶体管栅极电压，使得输出电压基于中间电压，第一晶体管的第一晶体管阈值电压和第二晶体管阈值 并且使得第一晶体管阈值电压和第二晶体管阈值电压的变化至少部分地相互抵消。
-
公开(公告)号：US08923439B1
公开(公告)日：2014-12-30
申请号：US13912905
申请日：2013-06-07
Applicant: Intel IP Corporation
Inventor： Chuanzhao Yu , Mark Kirschenmann
CPC classification number: H04L27/2092 , H03B28/00 , H03D7/12 , H03D7/165 , H04L27/0008 , H04L27/18 , H04L27/206 , H04L27/2071
Abstract: A method of performing complementary mixing may include performing an exclusive OR (XOR) function with respect to an I-channel symbol based on an oscillator signal to produce an I-channel output signal with bits that alternate between the I-channel symbol and a complement of the I-channel symbol in response to the oscillator signal rising and falling. The method may also include performing the XOR function with respect to a Q-channel symbol based on the oscillator signal to produce a Q-channel output signal with bits that alternate between the Q-channel symbol and a complement of the Q-channel symbol in response to the oscillator signal. Further, the method may include combining the I-channel output signal and the Q-channel output signal based on adding operations performed with respect to an I-channel extra bit signal, a Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal to generate a complementary mixed signal.
Abstract translation: 执行互补混合的方法可以包括基于振荡器信号相对于I信道符号执行异或（XOR）功能，以产生具有在I信道符号和补码之间交替的位的I信道输出信号 的I通道符号响应于振荡器信号的上升和下降。 该方法还可以包括基于振荡器信号执行关于Q信道符号的异或函数，以产生具有在Q信道符号和Q信道符号的互补之间交替的Q信道输出信号 响应振荡器信号。 此外，该方法可以包括基于对I信道额外位信号，Q信道额外位信号，I信道输出信号执行的相加操作来组合I信道输出信号和Q信道输出信号 和Q通道输出信号，以产生互补混合信号。
-
-
-
-
-
Search Results
6
records
(took 0.014 seconds)
