公开(公告)号：US08923439B1

公开(公告)日：2014-12-30

申请号：US13912905

申请日：2013-06-07

Applicant: Intel IP Corporation

Inventor： Chuanzhao Yu ,  Mark Kirschenmann

IPC: H04L27/20 ,  G10H1/00 ,  H03B28/00 ,  H04L27/00 ,  H04L27/18

CPC classification number: H04L27/2092 ,  H03B28/00 ,  H03D7/12 ,  H03D7/165 ,  H04L27/0008 ,  H04L27/18 ,  H04L27/206 ,  H04L27/2071

Abstract: A method of performing complementary mixing may include performing an exclusive OR (XOR) function with respect to an I-channel symbol based on an oscillator signal to produce an I-channel output signal with bits that alternate between the I-channel symbol and a complement of the I-channel symbol in response to the oscillator signal rising and falling. The method may also include performing the XOR function with respect to a Q-channel symbol based on the oscillator signal to produce a Q-channel output signal with bits that alternate between the Q-channel symbol and a complement of the Q-channel symbol in response to the oscillator signal. Further, the method may include combining the I-channel output signal and the Q-channel output signal based on adding operations performed with respect to an I-channel extra bit signal, a Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal to generate a complementary mixed signal.

Abstract translation: 执行互补混合的方法可以包括基于振荡器信号相对于I信道符号执行异或（XOR）功能，以产生具有在I信道符号和补码之间交替的位的I信道输出信号 的I通道符号响应于振荡器信号的上升和下降。 该方法还可以包括基于振荡器信号执行关于Q信道符号的异或函数，以产生具有在Q信道符号和Q信道符号的互补之间交替的Q信道输出信号 响应振荡器信号。 此外，该方法可以包括基于对I信道额外位信号，Q信道额外位信号，I信道输出信号执行的相加操作来组合I信道输出信号和Q信道输出信号 和Q通道输出信号，以产生互补混合信号。

公开(公告)号：US09337874B1

公开(公告)日：2016-05-10

申请号：US14575939

申请日：2014-12-18

Applicant: Intel IP Corporation

Inventor： Chuanzhao Yu ,  Mark Kirschenmann

IPC: H03C1/00 ,  H04B1/04 ,  H04L27/20 ,  H03M7/16 ,  H03M1/66

CPC classification number: H03M7/165 ,  H03M1/0863 ,  H03M1/687 ,  H03M1/804 ,  H04L27/00 ,  H04L27/20

Abstract: Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment, input binary bits are divided into two sets of bits, where one set is provided to a binary to thermometer coder to generate an output mixed with a clock signal to operatively provide a reverse order inverted bit pattern. The other set of binary bits is subject to exclusive-or processing such that processing of the two sets operatively provides a mixed hybrid code to be fed from high speed digital signal processor. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 提供高速数字信号处理器的装置和方法可以在基本上所有的数字发射机设计中实现。 在一个实施例中，输入二进制位被分成两组位，其中一组被提供给二进制到温度计编码器，以产生与时钟信号混合的输出，以可操作地提供反向反转位模式。 另一组二进制位被进行独占或处理，使得两组的处理可操作地提供要从高速数字信号处理器馈送的混合混合码。 公开了附加装置，系统和方法。