公开(公告)号：US10332854B2

公开(公告)日：2019-06-25

申请号：US15332533

申请日：2016-10-24

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Gabriel Z. Guevara ,  Xuan Li ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00

Abstract: A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

公开(公告)号：US20190096849A1

公开(公告)日：2019-03-28

申请号：US16197686

申请日：2018-11-21

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

公开(公告)号：US09865548B2

公开(公告)日：2018-01-09

申请号：US15158963

申请日：2016-05-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H01L21/00 ,  H01L23/49 ,  H01L21/76 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

公开(公告)号：US20170317019A1

公开(公告)日：2017-11-02

申请号：US15651826

申请日：2017-07-17

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/498 ,  H01L23/10 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US09741649B2

公开(公告)日：2017-08-22

申请号：US14586580

申请日：2014-12-30

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/10 ,  H01L23/13

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US09741620B2

公开(公告)日：2017-08-22

申请号：US14749529

申请日：2015-06-24

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/00 ,  H01L21/70 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US20170099474A1

公开(公告)日：2017-04-06

申请号：US15280661

申请日：2016-09-29

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H04N9/43 ,  H04N9/097 ,  H04N9/04 ,  G06T1/20 ,  H04N5/374 ,  H01L31/0232 ,  G02B27/10 ,  H01L27/146 ,  H01L31/0304 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/032 ,  H04N5/33 ,  H04N9/76

CPC classification number: H04N9/43 ,  G02B27/1013 ,  G06T1/20 ,  H01L27/1462 ,  H01L27/14634 ,  H01L27/14645 ,  H01L27/1465 ,  H01L27/14685 ,  H01L27/1469 ,  H01L31/02322 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/332 ,  H04N5/374 ,  H04N9/045 ,  H04N9/097 ,  H04N9/76

Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

公开(公告)号：US20160260687A1

公开(公告)日：2016-09-08

申请号：US14639942

申请日：2015-03-05

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Liang Wang

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/373 ,  H01L24/00 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/11334 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/2761 ,  H01L2224/32245 ,  H01L2224/81815 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/10253

Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

Abstract translation: 介绍了一种具有热控制功能的设备。 在一些实施例中，该装置包括位于堆叠中的多个管芯，每个管芯包括芯片，通过芯片的厚度相互连接，导电组合物的金属特征连接到芯片的底侧上的互连件和粘合剂 或底部填充层。 至少一个热传导层，其可以是热解石墨层，由碳纳米管形成的层或石墨烯层，被耦合在多个管芯中的一个的顶侧和邻接的管芯的底侧之间 堆栈 散热器可以耦合到导热层。

公开(公告)号：US09418924B2

公开(公告)日：2016-08-16

申请号：US14220912

申请日：2014-03-20

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Ron Zhang ,  Daniel Buckminster ,  Guilian Gao

IPC: H01L21/30 ,  H01L23/498 ,  H01L21/52 ,  H01L21/78 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L21/304 ,  H01L23/13

CPC classification number: H01L25/0657 ,  H01L21/304 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.

Abstract translation: 装置一般涉及集成电路封装。 在这种装置中，封装衬底具有从封装衬底的下表面延伸到封装衬底的上表面的第一多个通孔结构。 模具具有延伸到模具的下表面的第二多个通孔结构。 模具的下表面在集成电路封装中面向封装衬底的上表面。 封装基板不包括再分布层。 管芯和封装衬底彼此耦合。

公开(公告)号：US11302616B2

公开(公告)日：2022-04-12

申请号：US16288720

申请日：2019-02-28

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/498 ,  H01L21/56 ,  H01L25/16 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/13 ,  H01L25/065 ,  H01L23/10 ,  H01L23/00 ,  H01L23/14

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.