公开(公告)号：US20190096849A1

公开(公告)日：2019-03-28

申请号：US16197686

申请日：2018-11-21

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

公开(公告)号：US09825002B2

公开(公告)日：2017-11-21

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

公开(公告)号：US20170323867A1

公开(公告)日：2017-11-09

申请号：US15147807

申请日：2016-05-05

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/11426 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/27003 ,  H01L2224/2761 ,  H01L2224/27618 ,  H01L2224/2783 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/0645 ,  H01L2924/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

公开(公告)号：US20170141020A1

公开(公告)日：2017-05-18

申请号：US15086899

申请日：2016-03-31

Applicant: Invensas Corporation

Inventor： Grant Villavicencio ,  Sangil Lee ,  Roseann Alatorre ,  Javier A. Delacruz ,  Scott McGrath

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/56 ,  H01L23/053 ,  H01L21/48 ,  H01L23/31 ,  H01L23/043

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/043 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

公开(公告)号：US10325880B2

公开(公告)日：2019-06-18

申请号：US16197686

申请日：2018-11-21

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

公开(公告)号：US20180261556A1

公开(公告)日：2018-09-13

申请号：US15977905

申请日：2018-05-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Sangil Lee ,  Craig Mitchell ,  Gabriel Z. Guevara ,  Javier A. Delacruz

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  B23K1/00

CPC classification number: H01L23/562 ,  B23K1/0008 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012

Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

公开(公告)号：US20170018529A1

公开(公告)日：2017-01-19

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

Abstract translation: 微电子组件包括堆叠的半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 芯片端子可以沿着朝向相应芯片的边缘表​​面的方向从每个芯片的前表面处的触点延伸。 芯片堆叠以一定角度安装到基板，使得芯片的边缘表​​面面向基板的主表面，该主表面限定横向于即不平行于多个平行平面的第二平面。 导电材料将芯片端子与相应的衬底触点电连接。

公开(公告)号：US20190237437A1

公开(公告)日：2019-08-01

申请号：US16378921

申请日：2019-04-09

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

公开(公告)号：US09972582B2

公开(公告)日：2018-05-15

申请号：US15670382

申请日：2017-08-07

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Sangil Lee ,  Craig Mitchell ,  Gabriel Z. Guevara ,  Javier A. Delacruz

IPC: H01L23/488 ,  H01L23/00 ,  H01L21/48 ,  B23K1/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  B23K1/0008 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. The reinforcement layer adds structural support to the carrier or package, which can be very thin otherwise. In various embodiments, the addition of the reinforcement layer to the carrier or package reduces warpage of the carrier or package.

公开(公告)号：US20170148763A1

公开(公告)日：2017-05-25

申请号：US14952482

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/3107 ,  H01L24/02 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1815

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.