公开(公告)号：US12040284B2

公开(公告)日：2024-07-16

申请号：US17525559

申请日：2021-11-12

Applicant: Invensas LLC

Inventor： Patrick Variot ,  Hong Shen

IPC: H01L23/552 ,  H01L21/56 ,  H01L25/065 ,  H01Q1/38

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L25/0655 ,  H01Q1/38

Abstract: A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference (“EMI”) shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.

公开(公告)号：US20240339418A1

公开(公告)日：2024-10-10

申请号：US18747182

申请日：2024-06-18

Applicant: Invensas LLC

Inventor： Patrick Variot ,  Hong Shen

IPC: H01L23/552 ,  H01L21/56 ,  H01L25/065 ,  H01Q1/38

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L25/0655 ,  H01Q1/38

Abstract: A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference (“EMI”) shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.

公开(公告)号：US20240312928A1

公开(公告)日：2024-09-19

申请号：US18673099

申请日：2024-05-23

Applicant: Invensas LLC

Inventor： Patrick Variot ,  Hong Shen

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L23/31 ,  H01L23/5226

Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

公开(公告)号：US12021041B2

公开(公告)日：2024-06-25

申请号：US17509887

申请日：2021-10-25

Applicant: Invensas LLC

Inventor： Patrick Variot ,  Hong Shen

IPC: H01L23/52 ,  H01L23/31 ,  H01L23/522 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L23/31 ,  H01L23/5226

Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

公开(公告)号：US20230154862A1

公开(公告)日：2023-05-18

申请号：US17525559

申请日：2021-11-12

Applicant: Invensas LLC

Inventor： Patrick Variot ,  Hong Shen

IPC: H01L23/552 ,  H01Q1/38 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01Q1/38 ,  H01L25/0655 ,  H01L21/56

Abstract: A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference (“EMI”) shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.

公开(公告)号：US20230130259A1

公开(公告)日：2023-04-27

申请号：US18048378

申请日：2022-10-20

Applicant: INVENSAS LLC

Inventor： Belgacem Haba ,  Hong Shen ,  Patrick Variot ,  Rajesh Katkar

IPC: H01Q9/04 ,  H01Q1/52 ,  H01Q1/48 ,  H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through one or more of the conductive routing traces of the redistribution layer. When the antenna structure is separated from the system board, the integrated device die can be positioned between the antenna structure and the system board, and the integrated device die can be electrically coupled to the antenna structure at least partially through one or more of conductive routing traces of the system board and conductive wire of an interconnect structure between the system board and the antenna structure.