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    3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna
    1.
    发明授权
    3D-interconnect with electromagnetic interference (“EMI”) shield and/or antenna 有权

    公开(公告)号：US12040284B2

    公开(公告)日：2024-07-16

    申请号：US17525559

    申请日：2021-11-12

    Applicant: Invensas LLC

    Inventor： Patrick Variot ,  Hong Shen

    IPC: H01L23/552 ,  H01L21/56 ,  H01L25/065 ,  H01Q1/38

    CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L25/0655 ,  H01Q1/38

    Abstract: A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference (“EMI”) shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.

    3D memory circuit
    3.
    发明授权
    3D memory circuit 有权

    公开(公告)号：US11599299B2

    公开(公告)日：2023-03-07

    申请号：US17098299

    申请日：2020-11-13

    Applicant: Invensas LLC

    Inventor： Javier A. DeLaCruz ,  David E. Fisch

    IPC: G11C13/00 ,  G06F3/06 ,  G11C8/08 ,  G11C8/14 ,  G11C5/02 ,  H01L25/065 ,  G11C11/408 ,  G11C16/08 ,  G11C7/10

    Abstract: Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.

    WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING
    4.
    发明申请
    WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING 有权

    公开(公告)号：US20220320006A1

    公开(公告)日：2022-10-06

    申请号：US17721154

    申请日：2022-04-14

    Applicant: Invensas LLC

    Inventor： Shaowu Huang ,  Javier A. Delacruz

    IPC: H01L23/552

    Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

    Region shielding within a package of a microelectronic device
    6.
    发明授权
    Region shielding within a package of a microelectronic device 有权

    公开(公告)号：US12021041B2

    公开(公告)日：2024-06-25

    申请号：US17509887

    申请日：2021-10-25

    Applicant: Invensas LLC

    Inventor： Patrick Variot ,  Hong Shen

    IPC: H01L23/52 ,  H01L23/31 ,  H01L23/522 ,  H01L23/552

    CPC classification number: H01L23/552 ,  H01L23/31 ,  H01L23/5226

    Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

    Fine Pitch BVA Using Reconstituted Wafer With Area Array Accessible For Testing
    8.
    发明申请
    Fine Pitch BVA Using Reconstituted Wafer With Area Array Accessible For Testing 有权

    公开(公告)号：US20230005804A1

    公开(公告)日：2023-01-05

    申请号：US17865994

    申请日：2022-07-15

    Applicant: INVENSAS LLC

    Inventor： Rajesh Katkar

    IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/10 ,  H01L21/78

    Abstract: A microelectronic assembly having a first side and a second side opposite therefrom is disclosed. The microelectronic assembly may include a microelectronic element having a first face, a second face opposite the first face, a plurality of sidewalls each extending between the first and second faces, and a plurality of element contacts. The microelectronic assembly may also include an encapsulation adjacent the sidewalls of the microelectronic element. The microelectronic assembly may include electrically conductive connector elements each having a first end, a second end remote from the first end, and an edge surface extending between the first and second ends, wherein one of the first end or the second end of each connector element is adjacent the first side of the package. The microelectronic assembly may include a redistribution structure having terminals, the redistribution structure adjacent the second side of the package, the terminals being electrically coupled with the connector elements.

    MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER
    9.
    发明申请
    MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER 有权

    公开(公告)号：US20220375864A1

    公开(公告)日：2022-11-24

    申请号：US17835851

    申请日：2022-06-08

    Applicant: INVENSAS LLC

    Inventor： Liang Wang ,  Rajesh Katkar

    IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

    REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE
    10.
    发明公开
    REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240312928A1

    公开(公告)日：2024-09-19

    申请号：US18673099

    申请日：2024-05-23

    Applicant: Invensas LLC

    Inventor： Patrick Variot ,  Hong Shen

    IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

    CPC classification number: H01L23/552 ,  H01L23/31 ,  H01L23/5226

    Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

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