公开(公告)号：US20240347509A1

公开(公告)日：2024-10-17

申请号：US18636301

申请日：2024-04-16

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： HyeonChul LEE ,  KyoungHee PARK ,  KyungHwan KIM ,  SeungHyun LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/60 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/3121 ,  H01L23/60 ,  H01L24/94 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/1815

Abstract: A semiconductor package strip is provided. The semiconductor package strip includes: a substrate; a first set of electronic components and a first external connector attached on the substrate; a second set of electronic components and a second external connector attached on the substrate; wherein the first set of electronic components are adjacent to the second set of electronic components, and the first and second external connectors are disposed at two sides of the first and second sets of electronic components, respectively; an encapsulant layer formed on the substrate, wherein the encapsulant covers the first and second sets of electronic components but exposes the first and second external connectors; and a saw street in between the first and second sets of electronic components that allows for singulation of the semiconductor package strip at the saw street.

公开(公告)号：US20250038059A1

公开(公告)日：2025-01-30

申请号：US18749647

申请日：2024-06-21

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： HyeonChul LEE ,  KyoungHee PARK ,  KyungHwan KIM ,  SeungHyun LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/552 ,  H01L25/065

Abstract: A modular interconnection unit, a semiconductor package and a method for making the same are provided. The method includes: providing a first sub-package including a first substrate, at least one first interconnection pattern, and at least one first electronic component; mounting at least one modular interconnection unit on the first substrate, wherein the modular interconnection unit includes a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump raised from an upper surface of the dielectric layer, and a protection layer covering the conductive bump and having a flat upper surface, and the conductive via is electrically coupled with the first interconnection pattern; forming a first encapsulant on the upper surface of the first substrate; removing a portion of the protection layer to expose an upper surface of the conductive bump; and mounting a second sub-package above the first encapsulant.