公开(公告)号：US20240332114A1

公开(公告)日：2024-10-03

申请号：US18597878

申请日：2024-03-06

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YongMoo SHIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/27 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2225/06568

Abstract: A semiconductor device is provided. The semiconductor device includes a primary semiconductor die with a top surface, wherein the top surface comprising a first region and a second region besides the first region; an auxiliary semiconductor die attached onto the first region of the top surface of the primary semiconductor die; a thermally conductive laminated structure formed on the primary semiconductor die and the auxiliary semiconductor die, wherein the thermally conductive laminated structure at least partially covers the second region of the top surface of the primary semiconductor die, and at least partially covers a top surface of the auxiliary semiconductor die; and a heat spreader thermally coupled to the primary semiconductor die and the auxiliary semiconductor die through at least the thermally conductive laminated structure.

公开(公告)号：US20240120268A1

公开(公告)日：2024-04-11

申请号：US18475255

申请日：2023-09-27

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HunTaek LEE ,  KyoungHee PARK ,  SeongHwan PARK ,  YoungHoon JEON ,  HeeSoo LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/552 ,  H01L25/162

Abstract: A method for forming a shielding layer on a semiconductor device is disclosed. The semiconductor device comprises a bond pad formed on a front side of a substrate and extends to a first lateral surface of the substrate. The method comprises: etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface; attaching a filler onto the bond pad to fill the gap; and applying a shielding layer to a back side of the substrate.

公开(公告)号：US20240057249A1

公开(公告)日：2024-02-15

申请号：US18446487

申请日：2023-08-09

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YeJin PARK

IPC: H05K1/02 ,  H05K1/18 ,  H01L25/16 ,  H01L23/31 ,  H01L23/552 ,  H05K9/00 ,  H01L21/56 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H05K1/18 ,  H01L25/16 ,  H01L23/3121 ,  H01L23/552 ,  H05K9/0022 ,  H01L21/56 ,  H05K3/284 ,  H05K2201/2009 ,  H05K2201/10189 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: An electronic package comprises: a substrate comprising a first region and a second region adjacent to the first region in a lengthwise direction of the substrate; a first electronic component mounted on the substrate in the first region; a second electronic component mounted on the substrate in the second region, wherein the second electronic component does not occupy an entirety of the substrate in a widthwise direction of the substrate; and an encapsulant layer formed on the substrate, wherein at least the second electronic component is exposed from the encapsulant layer, and wherein the encapsulant layer extends from the first region to the second region to reinforce the substrate in both the first region and the second region.

公开(公告)号：US20250167168A1

公开(公告)日：2025-05-22

申请号：US18945569

申请日：2024-11-13

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HunTaek LEE ,  HeeSoo LEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01Q1/22

Abstract: A method for forming an electronic package is provided. The method comprises: providing a package substrate having a front surface and a back surface, wherein multiple sets of conductive pads are formed on the front surface of the package substrate; forming solder bumps on each set of conductive pads; attaching multiple front electronic components onto the front surface of the package substrate via solder bumps, wherein each of the multiple front electronic components is aligned with one set of the multiple sets of conductive pads; loading the package substrate on a bottom chase with the front surface facing upward; pressing, with a top chase, the front electronic components against the bottom chase to reshape the solder bumps and horizontally align top surfaces of the front electronic components with each other; and forming a front mold cap on the front surface to encapsulate the front electronic components.

公开(公告)号：US20250038059A1

公开(公告)日：2025-01-30

申请号：US18749647

申请日：2024-06-21

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： HyeonChul LEE ,  KyoungHee PARK ,  KyungHwan KIM ,  SeungHyun LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/552 ,  H01L25/065

Abstract: A modular interconnection unit, a semiconductor package and a method for making the same are provided. The method includes: providing a first sub-package including a first substrate, at least one first interconnection pattern, and at least one first electronic component; mounting at least one modular interconnection unit on the first substrate, wherein the modular interconnection unit includes a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump raised from an upper surface of the dielectric layer, and a protection layer covering the conductive bump and having a flat upper surface, and the conductive via is electrically coupled with the first interconnection pattern; forming a first encapsulant on the upper surface of the first substrate; removing a portion of the protection layer to expose an upper surface of the conductive bump; and mounting a second sub-package above the first encapsulant.

公开(公告)号：US20240105638A1

公开(公告)日：2024-03-28

申请号：US18469572

申请日：2023-09-19

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  SeongHwan PARK ,  InHo SEO ,  Bom LEE

IPC: H01L23/552 ,  B23K26/38 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/552 ,  B23K26/38 ,  H01L21/565 ,  H01L23/3121 ,  B23K2101/40

Abstract: A semiconductor device comprises a substrate comprising a conductive pattern and a conductive bar on the conductive pattern; at least one electronic component on the substrate; an encapsulant layer formed on the substrate and covering the at least one electronic component, a shielding layer extending at least partially over the substrate, the substrate comprises an opening over at least a portion of the conductive bar, the portion being exposed from the encapsulant layer and the substrate, the shielding layer extending within the opening and being electrically connected with the conductive bar in the opening, wherein the opening is adjacent to the encapsulant layer or is extended by an aperture in the encapsulant layer.

公开(公告)号：US20250140679A1

公开(公告)日：2025-05-01

申请号：US18929640

申请日：2024-10-29

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SangHoon LEE ,  SeungHyun LEE ,  HeeSoo LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/66 ,  H01L25/16

Abstract: A method for forming an electronic package assembly is provided. The method comprises: providing a base package substrate, wherein the base package substrate comprises a first package substrate, a second package substrate and an interconnect portion, and wherein first and second sets of conductive patterns are both formed on a front surface of the base package substrate; attaching a flexible cable linkage onto the front surface of the base package substrate and across the interconnect portion to electrically connect the first set of conductive patterns with the second set of conductive patterns; attaching a mold chase on the front surface of the base package substrate; forming a first mold cap within the first cavity and a second mold cap within the second cavity; and removing the interconnect portion from the base package substrate.

公开(公告)号：US20240421015A1

公开(公告)日：2024-12-19

申请号：US18746135

申请日：2024-06-18

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  YeJin PARK ,  HeeSoo LEE ,  HyunSu TAK ,  SangJun PARK

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/552 ,  H01L25/16 ,  H01R12/52

Abstract: A semiconductor package is disclosed. The semiconductor package comprises: a metal shim, a package substrate attached onto a front side of the metal shim, wherein the package substrate comprises an opening that passes therethrough; one or more electronic components mounted on the package substrate; an encapsulant layer partially formed on the package substrate to expose a region of the package substrate and the opening of the package substrate, wherein the encapsulant layer encapsulates the one or more electronic components on the package substrate; a first connector mounted in the exposed region of the package substrate; a second connector mounted in the encapsulant layer and on the package substrate; and a magnet mounted in the opening of the package substrate and extending from the metal shim through the package substrate and the encapsulant layer.

公开(公告)号：US20240404911A1

公开(公告)日：2024-12-05

申请号：US18670747

申请日：2024-05-22

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YongMoo SHIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a primary semiconductor die with a top surface, wherein the top surface comprising a first region and a second region besides the first region; an auxiliary semiconductor die attached on the first region of the top surface of the primary semiconductor die; a primary heat spreader assembly attached on the second region of the top surface of the primary semiconductor die; and an auxiliary heat spreader assembly attached on a top surface of the auxiliary semiconductor die, wherein the primary heat spreader assembly is thermally isolated from the auxiliary heat spreader assembly.

公开(公告)号：US20240355643A1

公开(公告)日：2024-10-24

申请号：US18639994

申请日：2024-04-19

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： Bom LEE ,  SeongHwan PARK ,  InHo SEO ,  SeungHyun LEE

IPC: H01L21/56 ,  H01L23/552

CPC classification number: H01L21/561 ,  H01L23/552

Abstract: A method for making a semiconductor device is provided. The method comprises: providing a package substrate strip mounted thereon multiple sets of first electronic components and multiple sets of second electronic components; forming an encapsulant layer on the package substrate strip that covers the multiple sets of first electronic components; forming a first shielding material by spray coating such that the first shielding material extends continuously from a top surface of the encapsulant layer to a top surface of the package substrate strip to cover at least a side surface of the encapsulant layer facing towards the multiple sets of second electronic components; singulating the package substrate strip into individual semiconductor packages with respective package substrates; and forming a second shielding material on the encapsulant layer by sputtering, wherein the second shielding material at least partially overlaps with the first shielding material.