公开(公告)号：US20060146027A1

公开(公告)日：2006-07-06

申请号：US11027268

申请日：2004-12-31

Applicant: James Tracy ,  James Zollo

Inventor： James Tracy ,  James Zollo

IPC: G09G5/00

CPC classification number: G06F3/0238 ,  G09F9/372 ,  H01H13/83 ,  H01H2215/00 ,  H01H2219/0023 ,  H01H2221/07

Abstract: A keypad assembly for an electronic device where characters are displayed on the buttons has a flexible display laminate (105). The flexible display laminate has a driver layer (106) on which button regions of conductor (300) are formed. Surrounding the button regions are conductorless regions (312). The lack of conductor in the surrounding regions allows appropriate tactile feedback to a user when the user depresses an actuating member (112), through which character formed by the flexible display laminate may be seen, actuating a popple switch circuit which allows the device to detect the button press.

Abstract translation: 用于电子设备的键盘组件，其中字符显示在按钮上，具有柔性显示层压板（105）。 柔性显示层叠体具有驱动层（106），导体（300）的按钮区域形成在其上。 围绕按钮区域是无导体区域（312）。 当用户按下致动构件（112）时，周围区域中的导体不足允许适当的触觉反馈，致动构件（112）可以看到由柔性显示层压板形成的特征，致动弹性开关电路，允许设备检测 按钮按下。

公开(公告)号：US20050243522A1

公开(公告)日：2005-11-03

申请号：US10837418

申请日：2004-04-30

Applicant: Ryan Nilsen ,  James Tracy ,  Nitin Desai ,  James Zollo

Inventor： Ryan Nilsen ,  James Tracy ,  Nitin Desai ,  James Zollo

IPC: G06F15/16 ,  H04B1/38 ,  H04M1/02 ,  H04M1/04 ,  H04M1/725 ,  H05K7/20

CPC classification number: H05K5/0091 ,  A45C2011/002 ,  A45C2011/003 ,  H04M1/0214 ,  H04M1/04 ,  H04M1/185 ,  H04M1/72575 ,  H04M2250/56

Abstract: A multi-purpose product packaging (100, 200) for an electronic host product (250) having its own casing can include an apparatus casing (110, 210) for removably and substantially encasing the electronic host product, circuitry (240) within the apparatus casing for providing at least one function to the electronic host product, and an interface (255) on the apparatus casing for enabling the at least one function to operate in conjunction with the electronic product. The apparatus casing can be made of recyclable products and the interface can form a portion of the circuitry within the apparatus casing. In one embodiment, the electronic host device can be a phone and the circuitry can provide any number of functions including the function of charging a power source within the phone.

Abstract translation: 用于具有其自身壳体的电子主机产品（250）的多用途产品包装（100,200）可以包括用于可移除地且基本上包围电子主机产品的装置壳体（110,210），该装置内的电路（240） 用于向所述电子主机产品提供至少一个功能的外壳，以及所述设备外壳上的用于使所述至少一个功能能够与所述电子产品一起操作的接口（255）。 设备外壳可以由可回收产品制成，并且接口可以在设备外壳内形成电路的一部分。 在一个实施例中，电子主机设备可以是电话，并且电路可以提供任何数量的功能，包括为电话内的电源充电的功能。

公开(公告)号：US20060103404A1

公开(公告)日：2006-05-18

申请号：US10989888

申请日：2004-11-12

Applicant: Nitin Desai ,  Paul Crandall ,  Ilya Lisak ,  Robert Mulligan ,  James Tracy ,  James Zollo

Inventor： Nitin Desai ,  Paul Crandall ,  Ilya Lisak ,  Robert Mulligan ,  James Tracy ,  James Zollo

IPC: G01R31/02

CPC classification number: G01R31/2874 ,  G01R31/287 ,  G01R31/2879 ,  G01R31/2884 ,  H05K1/0268 ,  H05K3/0011 ,  H05K2203/162

Abstract: A system includes a temperature chamber (100), a text fixture (402), a test coupon (400), a data acquisition unit (404), an ohmmeter (406) and a computer (410). The temperature chamber (100) provides temperature extremes to the test coupon (400). The test coupon (400) includes a substrate (314), one or more vias (418-429) and traces (402-412) connecting the vias. The data acquisition unit (404) continuously measures a resistance value of the circuit formed by the vias (418-429) and traces (402-412) during temperature cycling of the test coupon (400) held by the test fixture (402). The ohmmeter (406) measures the temperature of the test coupon (400) with a thermocouple. The data is used to detect failures of the materials in the test coupon (400) during the temperature cycling.

Abstract translation: 系统包括温度室（100），文本夹具（402），测试试样（400），数据获取单元（404），欧姆表（406）和计算机（410）。 温度室（100）向试样（400）提供极端温度。 试样（400）包括衬底（314），连接通孔的一个或多个通孔（418-429）和迹线（402-412）。 在由测试夹具（402）保持的测试试样（400）的温度循环期间，数据获取单元（404）连续地测量由通孔（418-429）和迹线（402-412）形成的电路的电阻值。 欧姆计（406）用热电偶测量试样（400）的温度。 该数据用于在温度循环期间检测试样（400）中的材料的失效。

公开(公告)号：US20050016763A1

公开(公告)日：2005-01-27

申请号：US10626058

申请日：2003-07-24

Applicant: James Zollo ,  John Arledge ,  John Barron ,  Gary Burhance ,  John Holley ,  Henry Liebman

Inventor： James Zollo ,  John Arledge ,  John Barron ,  Gary Burhance ,  John Holley ,  Henry Liebman

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H05K1/09 ,  H05K3/02

CPC classification number: H05K1/185 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A substrate assembly (10) and method of making same has at least one embedded component (25) in a via (24) of a substrate core (22) and includes a first adhesive layer (20) coupled to the substrate core, and a second adhesive layer (26) on at least portions of a top surface of the substrate core and above portions of the embedded component. The substrate assembly can further include a first conductive layer (18) adhered to the bottom surface of the substrate core and a second conductive layer (28) on the second adhesive layer. The substrate assembly can further include an interconnection (36) between a conductive surface of the embedded component and at least one among the first conductive layer and the second conductive layer. The interconnection can be formed through an opening (34) that at least temporarily exposes at least a conductive surface (32) of the embedded component.

Abstract translation: 衬底组件（10）及其制造方法在衬底芯（22）的通孔（24）中具有至少一个嵌入组件（25），并且包括耦合到衬底芯的第一粘合剂层（20）和 第二粘合剂层（26）在衬底芯的顶表面的至少部分上和嵌入部件的部分之上。 衬底组件还可以包括粘附到衬底芯的底表面的第一导电层（18）和第二粘合剂层上的第二导电层（28）。 衬底组件还可以包括在嵌入部件的导电表面与第一导电层和第二导电层中的至少一个之间的互连（36）。 互连可以通过至少暂时暴露嵌入式部件的导电表面（32）的开口（34）形成。

公开(公告)号：US20060215379A1

公开(公告)日：2006-09-28

申请号：US11089065

申请日：2005-03-24

Applicant: James Zollo ,  John Arledge ,  Nitin Desai

Inventor： James Zollo ,  John Arledge ,  Nitin Desai

IPC: B32B37/00 ,  H05K1/18

CPC classification number: H05K1/184 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49139

Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of preprocessed substrates.

Abstract translation: 多层衬底组件（80）包括在多个堆叠的预处理衬底内的至少一个嵌入部件（52）。 每个预处理衬底可以具有芯电介质（14），在芯电介质的相对侧上的图案化导电表面（12和16）以及至少两个相邻堆叠的预处理衬底中的每一个中的至少一个孔（18） 使得至少两个孔基本对准在彼此的顶部上，形成单个孔（19）。 组件还包括在相应的预处理衬底的顶表面和底表面之间的经处理的粘合剂层（48）。 将嵌入式部件放置在单个孔中，并在嵌入部件与单个孔的周围壁之间形成间隙（67＆66）。 当组件被偏压时，经处理的粘合剂层填充间隙以形成具有与多个预处理基板交叉的嵌入部件的组件。

公开(公告)号：US20050277307A1

公开(公告)日：2005-12-15

申请号：US10867345

申请日：2004-06-14

Applicant: James Zollo ,  Bonnie Bachman ,  Alan Beatty ,  Stephen Bozzone ,  Nitin Desai ,  Ronald Kelley ,  Rami Levy

Inventor： James Zollo ,  Bonnie Bachman ,  Alan Beatty ,  Stephen Bozzone ,  Nitin Desai ,  Ronald Kelley ,  Rami Levy

IPC: H01R4/64 ,  H01R12/16 ,  H01R33/00

CPC classification number: H01R4/64 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01R12/7076 ,  Y10T428/24033 ,  Y10T442/3504 ,  Y10T442/3659 ,  Y10T442/3683 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method and apparatus form electrical connections between electronic circuits and conductive threads (102, 104, 106, 108) that are interwoven into textile material (130). Electronic circuits (128), such as semiconductor dies, are connected to a carrier (132) and electrical connections (136) are made to conductive connection areas (110, 112, 114, 116) on the carrier (132). Conductive stitching (202, 204, 206, 208) provides electrical contacts for both the conductive connection areas (110, 112, 114, 116) on the carrier (132) and the conductive threads (102, 104, 106, 108) that are interwoven into the textile material (130). Optionally, a thin, flexible substrate material (132) is perforated during the stitching process.

Abstract translation: 一种方法和装置形成电子电路与交织到纺织材料（130）中的导电丝线（102,104,106,108）之间的电连接。 诸如半导体管芯的电子电路（128）连接到载体（132），并且电连接（136）被制成载体（132）上的导电连接区域（110,112,114,116）。 导电缝合（202,204,206,208）为载体（132）上的导电连接区域（110,112,114,116）和导电线（102,104,106,108）两者提供电接触，​​导电连接区域 交织到纺织材料（130）中。 可选地，在缝合过程期间穿孔薄的柔性基底材料（132）。

公开(公告)号：US20050016768A1

公开(公告)日：2005-01-27

申请号：US10626242

申请日：2003-07-24

Applicant: James Zollo ,  Nitin Desai

Inventor： James Zollo ,  Nitin Desai

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4623 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/096 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A multilayer circuit board (50) includes a plurality of substrate cores (34 and 44), an adhesive/bonding layer (55) between at least two among the plurality of substrate cores, and a microvia (35 and 45) in each of at least two of the plurality of substrate cores. The microvia includes a conductive interconnection (39) between a top conductive surface and a bottom conductive surface of each of the plurality of substrate cores and the microvia in a first substrate core is arranged to be inverted relative to a microvia in a second substrate core. The multilayer circuit board can further include a plated through-hole (54) through the plurality of substrate cores and the adhesive/bonding layer such that at least two among the top conductive surfaces (32 or 46) and the bottom conductive surfaces (36 or 42) of the plurality of substrate cores are connected.

Abstract translation: 多层电路板（50）包括多个基板芯（34和44），多个基板芯中的至少两个之间的粘合/粘合层（55）和每个基板芯中的微孔（35和45） 多个基板芯中的至少两个。 微孔包括在多个基板芯的每个的顶部导电表面和底部导电表面之间的导电互连（39），并且第一基板芯中的微孔被布置成相对于第二基板芯中的微孔而相反。 多层电路板还可以包括通过多个衬底芯和粘合/粘合层的电镀通孔（54），使得顶部导电表面（32或46）和底部导电表面（36或36）中的至少两个 连接多个基板芯的42）。