公开(公告)号：US20050016763A1

公开(公告)日：2005-01-27

申请号：US10626058

申请日：2003-07-24

Applicant: James Zollo ,  John Arledge ,  John Barron ,  Gary Burhance ,  John Holley ,  Henry Liebman

Inventor： James Zollo ,  John Arledge ,  John Barron ,  Gary Burhance ,  John Holley ,  Henry Liebman

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H05K1/09 ,  H05K3/02

CPC classification number: H05K1/185 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A substrate assembly (10) and method of making same has at least one embedded component (25) in a via (24) of a substrate core (22) and includes a first adhesive layer (20) coupled to the substrate core, and a second adhesive layer (26) on at least portions of a top surface of the substrate core and above portions of the embedded component. The substrate assembly can further include a first conductive layer (18) adhered to the bottom surface of the substrate core and a second conductive layer (28) on the second adhesive layer. The substrate assembly can further include an interconnection (36) between a conductive surface of the embedded component and at least one among the first conductive layer and the second conductive layer. The interconnection can be formed through an opening (34) that at least temporarily exposes at least a conductive surface (32) of the embedded component.

Abstract translation: 衬底组件（10）及其制造方法在衬底芯（22）的通孔（24）中具有至少一个嵌入组件（25），并且包括耦合到衬底芯的第一粘合剂层（20）和 第二粘合剂层（26）在衬底芯的顶表面的至少部分上和嵌入部件的部分之上。 衬底组件还可以包括粘附到衬底芯的底表面的第一导电层（18）和第二粘合剂层上的第二导电层（28）。 衬底组件还可以包括在嵌入部件的导电表面与第一导电层和第二导电层中的至少一个之间的互连（36）。 互连可以通过至少暂时暴露嵌入式部件的导电表面（32）的开口（34）形成。

公开(公告)号：US20080040921A1

公开(公告)日：2008-02-21

申请号：US11854098

申请日：2007-09-12

Applicant: JAMES ZOLLO ,  JOHN ARLEDGE ,  NITIN DESAI

Inventor： JAMES ZOLLO ,  JOHN ARLEDGE ,  NITIN DESAI

IPC: H05K3/30

CPC classification number: H05K1/184 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49139

Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.

Abstract translation: 多层衬底组件（80）包括在多个堆叠的预处理衬底内的至少一个嵌入部件（52）。 每个预处理衬底可以具有芯电介质（14），在芯电介质的相对侧上的图案化导电表面（12和16）以及至少两个相邻堆叠的预处理衬底中的每一个中的至少一个孔（18） 使得至少两个孔基本对准在彼此的顶部上，形成单个孔（19）。 组件还包括在相应的预处理衬底的顶表面和底表面之间的经处理的粘合剂层（48）。 将嵌入式部件放置在单个孔中，并在嵌入部件与单个孔的周围壁之间形成间隙（67＆66）。 当组件偏压时，经处理的粘合剂层填充间隙以形成具有与多个预处理衬底交叉的嵌入部件的组件。

公开(公告)号：US20060215379A1

公开(公告)日：2006-09-28

申请号：US11089065

申请日：2005-03-24

Applicant: James Zollo ,  John Arledge ,  Nitin Desai

Inventor： James Zollo ,  John Arledge ,  Nitin Desai

IPC: B32B37/00 ,  H05K1/18

CPC classification number: H05K1/184 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49139

Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of preprocessed substrates.

Abstract translation: 多层衬底组件（80）包括在多个堆叠的预处理衬底内的至少一个嵌入部件（52）。 每个预处理衬底可以具有芯电介质（14），在芯电介质的相对侧上的图案化导电表面（12和16）以及至少两个相邻堆叠的预处理衬底中的每一个中的至少一个孔（18） 使得至少两个孔基本对准在彼此的顶部上，形成单个孔（19）。 组件还包括在相应的预处理衬底的顶表面和底表面之间的经处理的粘合剂层（48）。 将嵌入式部件放置在单个孔中，并在嵌入部件与单个孔的周围壁之间形成间隙（67＆66）。 当组件被偏压时，经处理的粘合剂层填充间隙以形成具有与多个预处理基板交叉的嵌入部件的组件。

公开(公告)号：US20060024865A1

公开(公告)日：2006-02-02

申请号：US11238894

申请日：2005-09-29

Applicant: Jeffrey Underwood ,  John Arledge ,  Thomas Swirbel ,  Joaquin Barreto

Inventor： Jeffrey Underwood ,  John Arledge ,  Thomas Swirbel ,  Joaquin Barreto

IPC: H01L21/48 ,  H01L21/44

CPC classification number: H05K1/0218 ,  H01L2223/6622 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/113 ,  H05K3/4644 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2201/10553 ,  H05K2201/10969 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for shielding one or more circuits (21, 21′) of a printed circuit board includes depositing a layer of dielectric material (43) over a printed circuit board substrate (22) and the printed circuits (21, 21′), creating a trench-like opening (44) in the dielectric layer (43) such that the trench-like opening (44) surrounds the one or more circuits (21, 21′) to be shielded, depositing a layer of metal (27) over the layer of dielectric material (43) and within the trench-like openings (44), creating a solder pad (24) at each location where an electrical connection is to be made to the printed circuits (21, 21′) by removing a border of the metal layer (27) surrounding each connection location, and providing a microvia (25) through each solder pad (24) penetrating the dielectric layer (43) and terminating at the metal of the printed circuit (21, 21′).

Abstract translation: 用于屏蔽印刷电路板的一个或多个电路（21,21'）的方法包括在印刷电路板基板（22）和印刷电路（21,21'）之上沉积介电材料层（43），从而产生 电介质层（43）中的沟槽状开口（44），使得沟槽状开口（44）围绕要被屏蔽的一个或多个电路（21,21'），将金属层（27）沉积在 所述电介质材料层（43）并且在所述沟槽状开口（44）内，在每个位置处产生焊接焊盘（24），其中将通过去除所述印刷电路（21,21'）来形成电连接 围绕每个连接位置的金属层（27）的边界，以及通过穿过介电层（43）并终止在印刷电路（21,21'）的金属处的每个焊盘（24）提供微孔（25）。