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公开(公告)号：US20240363182A1
公开(公告)日：2024-10-31
申请号：US18766781
申请日：2024-07-09
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register circuit, including: a plurality of clock signal lines each supplying a clock pulse respectively; a plurality of cascade-connected register circuits including a top register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits.
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公开(公告)号：US20210191203A1
公开(公告)日：2021-06-24
申请号：US17192436
申请日：2021-03-04
Applicant: Japan Display Inc.
Inventor： Takahiro OCHIAI , Motoharu Miyamoto , Masahiro Hoshiba
IPC: G02F1/1362 , G02F1/1368 , G02F1/1335 , G02F1/1345 , H01L29/786 , G09G3/36 , H01L27/12
Abstract: A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.
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公开(公告)号：US20200321068A1
公开(公告)日：2020-10-08
申请号：US16906286
申请日：2020-06-19
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US20180114584A1
公开(公告)日：2018-04-26
申请号：US15848052
申请日：2017-12-20
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Hiroko SEHATA , Hiroyuki HIGASHIJIMA
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US20160246093A1
公开(公告)日：2016-08-25
申请号：US15145028
申请日：2016-05-03
Applicant: Japan Display Inc.
Inventor： Takahiro OCHIAI , Yuki KURAMOTO , Masahiro HOSHIBA
IPC: G02F1/133 , G02F1/1339 , G02F1/1337 , H01L29/417 , G02F1/1335 , G02F1/1343 , G09G3/36 , G11C19/28 , G02F1/1368 , G02F1/1333
CPC classification number: G02F1/13306 , G02F1/133345 , G02F1/133514 , G02F1/1337 , G02F1/1339 , G02F1/1341 , G02F1/134309 , G02F1/13454 , G02F1/136 , G02F1/1368 , G09G3/3648 , G09G2310/0286 , G11C19/28 , H01L29/41733 , H01L29/41758
Abstract: A liquid crystal display device includes a thin film transistor substrate, a counter substrate that faces the thin film transistor substrate, a liquid crystal composition that is arranged between the thin film transistor substrate and the counter substrate, an oriented film that arranges orientation of the liquid crystal composition contacting with the thin film transistor substrate, a seal material that seals the liquid crystal composition between the two substrates, and a driver circuit. The driver circuit has a light transmission area that is formed inside of the driver circuit, and is higher in light transmittance than an area in which a non-transparent conductive film forming the driver circuit is formed, and a high sealing property area in which the seal material and an insulating film come into direct contact with each other between the light transmission area and an outer edge of the thin film transistor substrate.
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Patent Agency Ranking
公开(公告)号：US20140375615A1
公开(公告)日：2014-12-25
申请号：US14478130
申请日：2014-09-05
Inventor： Takahiro OCHIAI , Mitsuru GOTO , Youzou NAKAYASU , Yuki OKADA , Naoki TAKADA
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3674 , G09G2300/0434
Abstract: A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.
Abstract translation: 提供了抑制门信号中的噪声的门信号线驱动电路和使用栅信号线驱动电路的显示装置。 提供给栅极信号线驱动电路的第一基本电路包括：高电压施加开关元件，其响应于信号高电平周期向栅极信号线施加HIGH电压;以及低电压施加开关电路，其向所述低电压施加开关元件施加低电压 门信号线响应于信号低电平周期。 响应于信号高电平周期，第一基本电路的低电压施加开关电路的开关基于施加到假设信号为高的第二基本电路的高电压施加开关元件的开关的信号而截止 比第一个基本电路早。
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公开(公告)号：US20140306947A1
公开(公告)日：2014-10-16
申请号：US14250487
申请日：2014-04-11
Applicant: Japan Display Inc.
Inventor： Motoharu MIYAMOTO , Takahiro OCHIAI , Hideo SATO
IPC: H03K17/16
CPC classification number: H03K17/162 , H03K17/16
Abstract: A gate signal line drive circuit and a display using the circuit, which suppress a leak current to reduce a power consumption. A gate signal line drive circuit that supplies a high voltage in a signal high period, and supplies a low voltage in a signal low period, the gate signal line drive circuit including: a high voltage supply switching element that turns on in response to the high period, supplies a voltage of a first basic clock signal to gate signal lines; a high voltage supply off control circuit that supplies a first low voltage to a switch of the high voltage supply switching element in response to the signal low period; and a low voltage supply switching circuit that supplies a second low voltage higher than the first low voltage to the gate signal lines in response to the signal low period.
Abstract translation: 门信号线驱动电路和使用该电路的显示器，其抑制泄漏电流以降低功耗。 一种栅极信号线驱动电路，其在信号高周期中提供高电压，并且在信号低电平周期中提供低电压，所述栅极信号线驱动电路包括：高电压电源开关元件，其响应于高电平而导通 向栅极信号线提供第一基本时钟信号的电压; 高压电源断开控制电路，其响应于所述信号低周期而向所述高压电源开关元件的开关提供第一低电压; 以及低电压电源开关电路，其响应于所述信号低周期而将高于所述第一低电压的第二低电压提供给所述栅极信号线。
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公开(公告)号：US20140267156A1
公开(公告)日：2014-09-18
申请号：US14201128
申请日：2014-03-07
Applicant: Japan Display Inc.
Inventor： Masayuki KOGA , Yukiya HIRABAYASHI , Takahiro OCHIAI
IPC: G06F3/044
CPC classification number: G06F3/0412 , G02F1/13338 , G06F3/0416 , G06F3/044 , G09G3/2092 , G09G2310/0286 , G09G2310/0291 , G11C19/184
Abstract: According to an aspect, a display device includes: a display unit that has a plurality of scanning signal lines to which a scanning signal is applied; a shift register that has a plurality of transfer circuits configured in a plurality of stages that perform a shift operation for temporarily storing a shift signal that has been input and sequentially transmitting the stored shift signal to a subsequent stage in synchronization with a clock signal having a discontinued period, and outputs the scanning signal to a scanning signal line corresponding to a transfer circuit that maintains the shift signal; and a signal line that transmits a holding potential signal for maintaining a potential of the shift signal to a transfer circuit that maintains the shift signal in the discontinued period of the clock signal.
Abstract translation: 根据本发明的一个方面，显示装置包括：显示单元，其具有施加扫描信号的多条扫描信号线; 一种移位寄存器，其具有多个传送电路，所述多个传送电路被配置为多个级，其执行用于临时存储已经输入的移位信号的移位操作，并且与具有所述移位寄存器的时钟信号同步地将所存储的移位信号顺序地发送到后续级 将扫描信号输出到与保持移位信号的传送电路对应的扫描信号线上; 以及信号线，其将用于保持移位信号的电位的保持电位信号发送到保持时钟信号的不连续时段中的移位信号的传送电路。
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公开(公告)号：US20200333673A1
公开(公告)日：2020-10-22
申请号：US16898645
申请日：2020-06-11
Inventor： Tohru SASAKI , Takahiro OCHIAI
IPC: G02F1/1362 , G02F1/1343 , G02F1/1333 , G02F1/1368 , G02F1/1335
Abstract: To form a sufficiently large storage capacitor, a liquid crystal display device includes a liquid crystal display panel having a first substrate, a second substrate, and a liquid crystal held between the first substrate and the second substrate, the liquid crystal display panel having multiple pixels arranged in matrix. The first substrate has, in a transmissive display area provided in each of the pixels, a laminated structure containing a first transparent electrode, a first insulating film, a second transparent electrode, a second insulating film, and a third transparent electrode which are laminated in this order. The first transparent electrode and the second transparent electrode are electrically insulated from each other and together form a first storage capacitor through the first insulating film, and the second transparent electrode and the third transparent electrode are electrically insulated from each other and together form a second storage capacitor through the second insulating film.
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公开(公告)号：US20200225518A1
公开(公告)日：2020-07-16
申请号：US16827386
申请日：2020-03-23
Inventor： Takahiro OCHIAI , Tohru SASAKI , Tetsuya NAGATA
IPC: G02F1/1339 , G02F1/1362 , G02F1/1368
Abstract: A column for defining the interval between a TFT substrate and an opposed substrate is formed at a crossing point between a drain line and a scanning line. At the crossing point where the column is formed, the drain line is formed to have a wider width to prevent light leakage. Further, at the crossing point where the column is formed, the scanning line is formed to have a narrower width to prevent increase of capacitance between the drain line and the scanning line. The column is formed at a crossing point corresponding to a specific color, e.g., a blue pixel B, so that a difference in transmittance and in characteristic of thin film transistors due to formation of the column is initially compensated.
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