公开(公告)号：US5024969A

公开(公告)日：1991-06-18

申请号：US484376

申请日：1990-02-23

Applicant: John J. Reche

Inventor： John J. Reche

IPC: H01L21/3105 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/481 ,  H01L21/31058 ,  H01L21/76825 ,  H01L21/76828 ,  Y10S148/046

Abstract: A method of fabricating high density multi-chip interconnects whereby one or more polymer layers thereon are cured at approximately room temperature utilizing high energy electron bombardment. The polymer layers, typically in the range of five to twenty microns in thickness, cured in accordance with the present invention, have very low ambiant temperature interlayer stresses, resulting in higher reliability and/or a wider operating temperature range for the finished high density multi-chip interconnect. In addition, curing times are grossly reduced, thereby making the manufacturing processing much more orderly and rapid. Interlayer adhesion of polymer layers cured in accordance with the present invention may be enhanced by the baking of the same at an elevated temperature below the glass transition temperture for the polymer. Various methods and parameters are disclosed.

Abstract translation: 一种制造高密度多芯片互连的方法，其中其上的一个或多个聚合物层在大约室温下利用高能电子轰击固化。 通常根据本发明固化的聚合物层的厚度通常在5至20微米的范围内具有非常低的环境温度层间应力，导致成品高密度多孔层的更高的可靠性和/或更宽的工作温度范围 芯片互连。 此外，固化时间大大减少，从而使制造加工更加有序，快速。 根据本发明固化的聚合物层的层间粘合可以通过在高于聚合物的玻璃化转变温度的高温下进行烘烤来提高。 公开了各种方法和参数。

公开(公告)号：US5023205A

公开(公告)日：1991-06-11

申请号：US344252

申请日：1989-04-27

Applicant: John J. Reche

Inventor： John J. Reche

IPC: H01L21/48 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L21/4846 ,  H05K3/328 ,  H05K3/4007 ,  H05K3/4644 ,  Y10S148/02

Abstract: Hybrid circuit structures and methods of fabrication which result in improved manufacturing yields and reliability in use are disclosed. The methods disclosed include methods of forming on the hybrid circuit substrate, a ground plane, bonding pads, and interconnects, which minimize the likelihood of forming catastrophic defects in various insulation layers during the manufacturing processing, which minimize the likelihood of damage to the bonding pads when bonding integrated circuit leads thereto, and which minimize the thermal stressing of a finished product due to the differential expansion between the various layers making up the same. Alternate methods and structures are disclosed.

Abstract translation: 公开了混合电路结构和制造方法，其导致改进的制造产量和使用的可靠性。 所公开的方法包括在混合电路衬底上形成的方法，接地平面，接合焊盘和互连，其最小化在制造处理期间在各种绝缘层中形成灾难性缺陷的可能性，从而最小化损坏接合焊盘的可能性 当结合集成电路通向其时，由于构成相同的各层之间的差异扩大，使成品的热应力最小化。 公开了替代方法和结构。

公开(公告)号：US5282922A

公开(公告)日：1994-02-01

申请号：US850382

申请日：1992-03-11

Applicant: John J. Reche

Inventor： John J. Reche

IPC: H01L21/48 ,  H01L23/14 ,  H01L25/16 ,  H01L21/00

CPC classification number: H01L23/147 ,  H01L21/4846 ,  H01L25/16 ,  H01L2924/0002 ,  Y10S148/103 ,  Y10S148/106

Abstract: Hybrid circuit structures and methods of fabrication particularly suitable for the fabrication of high density multi-layer interconnects utilizing silicon substrates are disclosed. In accordance with the method, a layer of alumina is put down over the silicon substrate, typically having an oxide layer thereover, which layer of alumina acts as a blocking barrier to any subsequent plasma etching process for etching polymer layers thereover during the subsequent high density multilayer interconnect fabrication steps. Various representative high density multi-layer interconnect structures on silicon substrates and methods of forming the same are disclosed, including the inclusion of an adhesion enhancement layer over the layer of alumina to enhance the adhesion of a polymer which would not otherwise adhere well directly to the layer of alumina.

Abstract translation: 公开了特别适用于利用硅衬底制造高密度多层互连的混合电路结构和制造方法。 根据该方法，将氧化铝层放置在硅衬底上，通常在其上具有氧化物层，该氧化铝层用作随后的高密度中随后蚀刻聚合物层的任何后续等离子体蚀刻工艺的阻挡屏障 多层互连制造步骤。 公开了硅衬底上的各种代表性的高密度多层互连结构及其形成方法，包括在氧化铝层上包含粘合增强层，以增强聚合物的粘附性，该聚合物不会以其它方式很好地直接粘附到 氧化铝层。

公开(公告)号：US5196376A

公开(公告)日：1993-03-23

申请号：US662748

申请日：1991-03-01

Applicant: John J. Reche

Inventor： John J. Reche

IPC: H01L21/312 ,  H01L21/3213 ,  H01L21/48 ,  H05K3/00 ,  H05K3/06

CPC classification number: H05K3/061 ,  H01L21/312 ,  H01L21/32139 ,  H01L21/4846 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K3/0041 ,  Y10S438/94

Abstract: A laser lithography process for semiconductor interconnect and semiconductor manufacture having the advantages of non-contact printing processes and being much faster than prior art laser lithography processes is disclosed. In accordance with the process, a metal layer to be patterned either for use as a patterned metal layer or as a mask for patterning a layer therebelow, such as a think polyimide layer, is first coated with a very thin layer of polymer evaporated as a monomer using a vapor deposition process. This provides a very thin layer of polymer over the metal layer, which thin polymer layer is readily and quickly patterned by laser to provide a mask for the subsequent chemical etching of the metal layer. The vapor deposited polymer layer, while being very thin and thus readily removed by laser, is also substantially fault free, thereby providing a high-quality mask for the chemical etching process free of any possible damage from ordinary sources such as mask aligners, etc., yet being readily removed when desired such as by way of example, by plasma etching thereof. Various methods and applications are disclosed.

Abstract translation: 公开了一种用于半导体互连和半导体制造的激光光刻工艺，其具有非接触印刷工艺的优点并且比现有技术的激光光刻工艺快得多。 根据该方法，首先将要被图案化的图案化的金属层用作图案化金属层或作为用于图案化层的掩模，例如思亚酰胺层，涂覆有非常薄的作为 单体使用气相沉积工艺。 这在金属层上提供了非常薄的聚合物层，该薄层聚合物层通过激光容易且快速地构图，以提供用于金属层的后续化学蚀刻的掩模。 气相沉积聚合物层虽然非常薄且因此容易通过激光去除，但也基本上是无缺陷的，从而为化学蚀刻工艺提供了高质量的掩模，没有普通来源（例如掩模对准器等）的任何可能的损坏。 ，但是如果需要的话，例如通过等离子体蚀刻就容易除去。 公开了各种方法和应用。

公开(公告)号：US5030318A

公开(公告)日：1991-07-09

申请号：US413944

申请日：1989-09-28

Applicant: John J. Reche

Inventor： John J. Reche

IPC: G01R3/00

CPC classification number: G01R3/00

Abstract: Methods of making an electrical probe diaphragm wherein the diaphragm is integral with the surrounding support structure, which methods are conducive to the fabrication probing circuitry integral therewith. In accordance with the method, a substrate having first and second surfaces is coated on the first surface with an uncured polymer film in the polymer cured. Also, one or more pattern metalization layers are provided, typical over the polymer layer and extending peripherally outward to contact regions near the periphery of the substrate, preferably accessible from the second side of the substrate so contact with the pattern metalization layer or layers forming the probe circuitry may be made from the second side of the substrate. The central region of the substrate thereafter removed, typically by etching from the second side of the substrate so as to remove the support for the polymer layer and metalization layers in that region, leaving the same as a diaphragm substantially integral with the remaining peripheral region of the substrate. Details of the methods and alternates thereto are disclosed.

Abstract translation: 制造电探测光阑的方法，其中光阑与周围的支撑结构是一体的，哪些方法有助于与其集成的制造探测电路。 根据该方法，在固化的聚合物中，在第一表面上涂布未固化的聚合物膜的具有第一表面和第二表面的基材。 而且，提供了一个或多个图案金属化层，典型地在聚合物层上方并且周向地向外延伸到基板周边附近的接触区域，优选从基板的第二侧可接触，从而与形成图案金属化层 探针电路可以从衬底的第二侧制成。 通常通过从衬底的第二侧蚀刻来除去衬底的中心区域，以除去该区域中的聚合物层和金属化层的支撑体，留下与隔膜的剩余外围区域基本上成一体的隔膜 底物。 公开了其方法及其替代的细节。