公开(公告)号：US20230063072A1

公开(公告)日：2023-03-02

申请号：US17651094

申请日：2022-02-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinji SAITO ,  Yoichiro KURITA ,  Rei HASHIMOTO ,  Kei KANEKO ,  Takayoshi FUJII

IPC: H01S5/026 ,  H01S5/34 ,  H01S5/11 ,  H01S5/183 ,  H01S5/42 ,  A61B5/145 ,  A61B5/1455

Abstract: An analysis device includes a substrate including a first surface, and a second surface positioned at a side opposite to the first surface; a light source part located at the first surface of the substrate, the light source part including a quantum cascade laser; a light detector located at the first surface of the substrate; and a wiring part located at the first surface of the substrate, the wiring part being electrically connected with the light source part and the light detector.

公开(公告)号：US20220107397A1

公开(公告)日：2022-04-07

申请号：US17471020

申请日：2021-09-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masatoshi HIRONO ,  Yoichiro KURITA ,  Hideto FURUYAMA

IPC: G01S7/481 ,  G02B27/30 ,  G02B5/04

Abstract: According to one embodiment, a LIDAR system includes a laser oscillator, a collimator lens, a scan device, and a prism. The laser oscillator emits laser light. The collimator lens converts the laser light to parallel light. The scan device includes a reflective surface on which the laser light that has passed through the collimator lens is reflected, and a rotation device rotating the reflective surface around a rotation axis. The prism has a first surface and a second surface, and emits, from the second surface, the laser light that has been reflected on the reflective surface to enter the first surface.

公开(公告)号：US20180128998A1

公开(公告)日：2018-05-10

申请号：US15688717

申请日：2017-08-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideto FURUYAMA ,  Yoichiro KURITA ,  Hiroshi UEMURA ,  Fumitaka ISHIBASHI

IPC: G02B6/42 ,  G02B6/32 ,  G02B6/34

CPC classification number: G02B6/424 ,  G02B6/32 ,  G02B6/34 ,  G02B6/4239 ,  G02B6/4251 ,  G02B6/4256 ,  G02B6/4274

Abstract: An optical semiconductor module includes a resin body having a first surface and an opposed second surface, an optical device having a third surface and a fourth surface opposite the third surface, the optical device comprising an optical element located at the fourth surface, the optical element capable of at least one of receiving light from, and transmitting light through, the third surface, a first terminal located at the first surface of the resin body, and an electrical connection between the first terminal and the optical device, the electrical connection embedded in the resin body.

公开(公告)号：US20170287889A1

公开(公告)日：2017-10-05

申请号：US15630496

申请日：2017-06-22

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazushige KAWASAKI ,  Yoichiro KURITA

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/80203 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/80001 ,  H01L2224/81 ,  H01L2924/014

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

公开(公告)号：US20150069596A1

公开(公告)日：2015-03-12

申请号：US14190921

申请日：2014-02-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazushige KAWASAKI ,  Yoichiro KURITA ,  Satoshi TSUKIYAMA ,  Masayuki MIURA

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4817 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion.

Abstract translation: 根据一个实施例，半导体器件包括金属板，多个半导体芯片，绝缘层，布线层，外部连接端子和密封树脂部分。 金属板包括第一表面，并且多个半导体芯片层叠在金属板的第二表面上。 绝缘层和布线层设置在半导体芯片上。 外部连接端子设置在绝缘层和布线层上。 密封树脂部分在暴露金属板的第一表面的同时密封多个半导体芯片。 金属板的至少一对相对的外周面被密封树脂​​部分覆盖。

公开(公告)号：US20200051953A1

公开(公告)日：2020-02-13

申请号：US16657618

申请日：2019-10-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yoichiro KURITA

IPC: H01L23/00 ,  H01L21/67

Abstract: A bonding method of a first member includes arranging an activated front surface of a first member and an activated front surface of a second member so as to face each other with a back surface of the first member attached to a sheet, pushing a back surface of the first member through the sheet to closely attach the activated front surface of the first member and the activated front surface of the second member, and stripping the sheet from the back surface of the first member while maintaining a state in which the activated front surface of the first member is closely attached to the activated front surface of the second member.

公开(公告)号：US20160365336A1

公开(公告)日：2016-12-15

申请号：US15249146

申请日：2016-08-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TSUKIYAMA ,  Hideko MUKAIDA ,  Yoichiro KURITA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/181 ,  H05K1/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.

Abstract translation: 一种半导体器件包括：包括无机保护膜的第一半导体芯片，包括有机保护膜的第二半导体芯片和再布线层，所述第二半导体芯片通过硅通孔电连接到第一半导体芯片， 凸起连接，包括无机保护膜的第三半导体芯片，通过再布线层与第二半导体芯片电连接的第三半导体芯片和凸块连接，填充在第一半导体芯片和第二半导体之间的第一树脂层 第一树脂层与无机保护膜接触，第二树脂层填充在第二半导体芯片和第三半导体芯片之间，第二树脂层与有机保护膜和无机保护膜接触。

公开(公告)号：US20160268232A1

公开(公告)日：2016-09-15

申请号：US14839676

申请日：2015-08-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yoichiro KURITA

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81065 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.

Abstract translation: 根据一个实施例，半导体器件包括包括多个半导体芯片并且具有第一宽度的层压体，至少部分半导体芯片包括延伸穿过半导体芯片的电极，半导体芯片被堆叠并彼此连接通过 电极; 设置在所述层压体的第一表面上并且具有大于所述第一宽度的第二宽度的硅基板; 设置在所述层叠体的第二面上的布线层; 以及设置在层叠体周围的树脂。

公开(公告)号：US20160079184A1

公开(公告)日：2016-03-17

申请号：US14636071

申请日：2015-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TSUKIYAMA ,  Hideko MUKAIDA ,  Yoichiro KURITA

IPC: H01L23/00 ,  H01L23/12 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/181 ,  H05K1/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.

Abstract translation: 一种半导体器件包括：包括无机保护膜的第一半导体芯片，包括有机保护膜的第二半导体芯片和再布线层，所述第二半导体芯片通过硅通孔电连接到第一半导体芯片， 凸起连接，包括无机保护膜的第三半导体芯片，通过再布线层与第二半导体芯片电连接的第三半导体芯片和凸块连接，填充在第一半导体芯片和第二半导体之间的第一树脂层 第一树脂层与无机保护膜接触，第二树脂层填充在第二半导体芯片和第三半导体芯片之间，第二树脂层与有机保护膜和无机保护膜接触。

公开(公告)号：US20220077081A1

公开(公告)日：2022-03-10

申请号：US17194031

申请日：2021-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Yoichiro KURITA ,  Takanobu KAMAKURA ,  Masayuki SUGIURA ,  Yoshiaki AIZAWA

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.