公开(公告)号：US12026034B1

公开(公告)日：2024-07-02

申请号：US17472330

申请日：2021-09-10

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F1/32 ,  G06F1/329 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  G06N20/00

CPC classification number: G06F1/329 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  G06N20/00 ,  H01L2924/14335 ,  H01L2924/1438 ,  H01L2924/1441

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US12019492B1

公开(公告)日：2024-06-25

申请号：US17408326

申请日：2021-08-20

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F1/3203 ,  H01L23/367 ,  H01L23/538 ,  H02M3/10

CPC classification number: G06F1/3203 ,  H01L23/3677 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H02M3/10 ,  H01L2924/37001

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US11829699B1

公开(公告)日：2023-11-28

申请号：US17407094

申请日：2021-08-19

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F30/398 ,  G06F1/20 ,  G06F30/392 ,  G06F30/3308 ,  G06F30/367 ,  G06F119/06 ,  G06F119/02 ,  G06F115/10 ,  G06F117/08 ,  G06F119/08

CPC classification number: G06F30/398 ,  G06F1/206 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/392 ,  G06F2115/10 ,  G06F2117/08 ,  G06F2119/02 ,  G06F2119/06 ,  G06F2119/08

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US11373727B1

公开(公告)日：2022-06-28

申请号：US17351047

申请日：2021-06-17

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni ,  Amrita Mathuriya

IPC: G11C7/10 ,  G11C8/06 ,  G11C29/44 ,  G11C11/4091 ,  G11C11/4093 ,  G11C29/18

Abstract: Logic (apparatus and/or software) is provided that separates read and restore operations. When a read is completed, the read data is stored in a restore buffer allowing other latency critical operations such as reads to be serviced before the restore. Deferring restore operations minimizes latency and burst bandwidth for reads and minimizes the performance impact of the non-critical restore operations.

公开(公告)号：US12001266B1

公开(公告)日：2024-06-04

申请号：US17408323

申请日：2021-08-20

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F1/32 ,  G06F1/329 ,  G11C5/04 ,  G11C11/00 ,  H01L25/16 ,  G06N20/00

CPC classification number: G06F1/329 ,  G11C5/04 ,  G11C11/005 ,  H01L25/162 ,  G06N20/00 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2924/1441

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US11899613B1

公开(公告)日：2024-02-13

申请号：US17408251

申请日：2021-08-20

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F15/78 ,  G06F9/48 ,  G06F9/54 ,  G06F9/50

CPC classification number: G06F15/7825 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/54 ,  G06F15/7821 ,  G06F15/7842

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US11790969B1

公开(公告)日：2023-10-17

申请号：US17344815

申请日：2021-06-10

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: G11C11/22 ,  G06F12/02 ,  G11C13/00 ,  G11C11/02

CPC classification number: G11C11/221 ,  G06F12/0246 ,  G11C11/02 ,  G11C11/225 ,  G11C13/0002 ,  G11C13/0035 ,  G06F2212/7202 ,  G06F2212/7211

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

公开(公告)号：US11295796B1

公开(公告)日：2022-04-05

申请号：US17344817

申请日：2021-06-10

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16 ,  G11C16/10

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

公开(公告)号：US20240402908A1

公开(公告)日：2024-12-05

申请号：US18806592

申请日：2024-08-15

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F3/06 ,  G06F12/0817 ,  G06N20/00

Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

公开(公告)号：US12086410B1

公开(公告)日：2024-09-10

申请号：US17229754

申请日：2021-04-13

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/0817 ,  G06N20/00

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0828 ,  G06N20/00 ,  G06F2212/621

Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.