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    CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE
    1.
    发明申请
    CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE 有权
    时钟同步电路和半导体器件

    公开(公告)号：US20140043073A1

    公开(公告)日：2014-02-13

    申请号：US13962087

    申请日：2013-08-08

    Applicant: LAPIS SEMICONDUCTOR CO., LTD.

    Inventor： Kenji ARAI

    IPC: H03L7/00

    CPC classification number: H04L27/066 ,  G06F1/12 ,  G06F13/42 ,  H03K3/35606 ,  H03K3/356156 ,  H03K19/0013 ,  H03K19/018521 ,  H03K19/096 ,  H03L7/00 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/033

    Abstract: A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current.

    Abstract translation: 时钟同步电路被配置为根据输入时钟信号捕获输入数据位，并且同步并输出输入数据位。 时钟同步电路包括用于根据输入时钟信号产生内部时钟信号并将内部时钟信号发送到时钟线的时钟缓冲器。 时钟同步电路还包括用于在内部时钟信号的边缘定时处捕获并输出输入数据位的D触发器。 时钟缓冲器包括逆变器芯部分和电流抑制部分。 逆变器芯部被配置为通过交替地向时钟线提供电流并根据输入时钟信号从时钟线引出电流来产生内部时钟信号。 电流抑制部被配置为抑制电流量。

    CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE
    4.
    发明申请
    CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开
    时钟同步电路和半导体器件

    公开(公告)号：US20150124917A1

    公开(公告)日：2015-05-07

    申请号：US14592054

    申请日：2015-01-08

    Applicant: LAPIS SEMICONDUCTOR CO., LTD.

    Inventor： Kenji ARAI

    IPC: H04L27/06

    CPC classification number: H04L27/066 ,  G06F1/12 ,  G06F13/42 ,  H03K3/35606 ,  H03K3/356156 ,  H03K19/0013 ,  H03K19/018521 ,  H03K19/096 ,  H03L7/00 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/033

    Abstract: A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current.

    Abstract translation: 时钟同步电路被配置为根据输入时钟信号捕获输入数据位，并且同步并输出输入数据位。 时钟同步电路包括用于根据输入时钟信号产生内部时钟信号并将内部时钟信号发送到时钟线的时钟缓冲器。 时钟同步电路还包括用于在内部时钟信号的边缘定时处捕获并输出输入数据位的D触发器。 时钟缓冲器包括逆变器芯部分和电流抑制部分。 逆变器芯部被配置为通过交替地向时钟线提供电流并根据输入时钟信号从时钟线引出电流来产生内部时钟信号。 电流抑制部被配置为抑制电流量。

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