公开(公告)号：US20240143060A1

公开(公告)日：2024-05-02

申请号：US18408548

申请日：2024-01-09

Applicant: MAXLINEAR, INC.

Inventor： Chunfeng Hu ,  Rajan Raghvendra

IPC: G06F1/324 ,  G06F1/08 ,  H03K5/135

CPC classification number: G06F1/324 ,  G06F1/08 ,  H03K5/135 ,  G06F1/3203

Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

公开(公告)号：US11868194B2

公开(公告)日：2024-01-09

申请号：US17806934

申请日：2022-06-14

Applicant: MAXLINEAR, INC.

Inventor： Chunfeng Hu ,  Rajan Raghvendra

IPC: G06F1/00 ,  G06F1/324 ,  H03K5/135 ,  G06F1/08 ,  G06F1/3203

CPC classification number: G06F1/324 ,  G06F1/08 ,  H03K5/135 ,  G06F1/3203

Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

公开(公告)号：US20220391000A1

公开(公告)日：2022-12-08

申请号：US17806934

申请日：2022-06-14

Applicant: MAXLINEAR, INC.

Inventor： Chunfeng Hu ,  Rajan Raghvendra

IPC: G06F1/324 ,  H03K5/135 ,  G06F1/08

Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.

公开(公告)号：US11360539B2

公开(公告)日：2022-06-14

申请号：US16134174

申请日：2018-09-18

Applicant: MaxLinear, Inc.

Inventor： Chunfeng Hu ,  Rajan Raghvendra

IPC: G06F1/00 ,  G06F1/324 ,  H03K5/135 ,  G06F1/08 ,  G06F1/3203

Abstract: Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.