公开(公告)号：US11153222B2

公开(公告)日：2021-10-19

申请号：US16410112

申请日：2019-05-13

Applicant: MAXLINEAR, INC.

Inventor： Ingo Volkening ,  Hak Keong Sim ,  Ritesh Banerjee

IPC: H04L12/863 ,  H04L12/935 ,  H04L12/721 ,  H04L12/933 ,  H04L29/06 ,  H04L12/54 ,  H04L29/08

Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.

公开(公告)号：US11550877B2

公开(公告)日：2023-01-10

申请号：US15303852

申请日：2015-04-15

Applicant: MaxLinear, Inc.

Inventor： Ingo Volkening ,  Ritesh Banerjee ,  Olaf Wachendorf ,  Stephan Pruecklmayer

IPC: G06F21/10 ,  G06F21/57 ,  H04L9/32 ,  H04L9/40

Abstract: First transistor logic is arranged by a first logic provider in circuit form and provides a minimum of functionality of the semiconductor device employed to bring up the semiconductor device, wherein the minimum of functionality is encrypted using a first encryption key. Second transistor logic is arranged by a second logic provider, different than the first logic provider, in circuit form to include security keys capable to perform cryptographic capabilities using a second encryption key. The second transistor logic further includes functionality that completes the semiconductor device as a chip device and is ready to process secure communication signals.