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公开(公告)号：US20240356681A1
公开(公告)日：2024-10-24
申请号：US18762573
申请日：2024-07-02
Applicant: MaxLinear, Inc.
Inventor： Ingo Volkening , Amos Klimker , Rafi Abraham
IPC: H04L1/1829 , H04L1/1607
CPC classification number: H04L1/1841 , H04L1/1642
Abstract: A system may include primary and secondary integrated circuits. The primary integrated circuit may receive a first subset of data packets associated with a first set of sequence numbers. The secondary integrated circuit may receive a second subset of data packets associated with a second set of sequence numbers. The primary integrated circuit is configured to manage the first set of sequence numbers and the second set of sequence numbers on behalf of the secondary integrated circuit and for the system.
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公开(公告)号：US20220038385A1
公开(公告)日：2022-02-03
申请号：US17451487
申请日：2021-10-19
Applicant: MAXLINEAR, INC.
Inventor： Ingo Volkening , Hak Keong Sim , Rush Banerjee
IPC: H04L12/863 , H04L12/935 , H04L12/721 , H04L12/933 , H04L29/06
Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.
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公开(公告)号：US12028168B2
公开(公告)日：2024-07-02
申请号：US17659281
申请日：2022-04-14
Applicant: MAXLINEAR, INC.
Inventor： Ingo Volkening , Amos Klimker , Rafi Abraham
IPC: H04L1/1829 , H04L1/1607
CPC classification number: H04L1/1841 , H04L1/1642
Abstract: A system may include primary and secondary integrated circuits. The primary integrated circuit may receive a first subset of data packets associated with a first set of sequence numbers. The secondary integrated circuit may receive a second subset of data packets associated with a second set of sequence numbers. The primary integrated circuit is configured to manage the first set of sequence numbers and the second set of sequence numbers on behalf of the secondary integrated circuit and for the system.
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公开(公告)号：US20240119022A1
公开(公告)日：2024-04-11
申请号：US18484443
申请日：2023-10-10
Applicant: MaxLinear, Inc.
Inventor： Isaac Sitton , Ingo Volkening , Oren Bakshe , Pinaki Shankar Chanda , Michael Ray Ham
IPC: G06F13/42
CPC classification number: G06F13/4282
Abstract: A method includes obtaining data to process using at least one data transform operation. The method further includes determining a processing path for the data to traverse at least a first data transform engine and a second data transform engine. The method also includes directing the data to the first data transform engine. The first data transform engine is to perform a first data transform operation on the data. The method further includes directing the data to the second data transform engine, the second data transform engine to perform a second data transform operation on the data.
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公开(公告)号：US20220337354A1
公开(公告)日：2022-10-20
申请号：US17659281
申请日：2022-04-14
Applicant: MAXLINEAR, INC.
Inventor： Ingo Volkening , Amos Klimker , Rafi Abraham
Abstract: A system may include primary and secondary integrated circuits. The primary integrated circuit may receive a first subset of data packets associated with a first set of sequence numbers. The secondary integrated circuit may receive a second subset of data packets associated with a second set of sequence numbers. The primary integrated circuit is configured to manage the first set of sequence numbers and the second set of sequence numbers on behalf of the secondary integrated circuit and for the system.
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Patent Agency Ranking
公开(公告)号：US20250158730A1
公开(公告)日：2025-05-15
申请号：US19012638
申请日：2025-01-07
Applicant: MaxLinear, Inc.
Inventor： Chun Feng Hu , Ingo Volkening
Abstract: Various examples of the present disclosure relate to a transmitter apparatus, device, method, and computer program, to a receiver apparatus, device, method, and computer program, and to corresponding source and destination devices and communication devices. The transmitter apparatus comprises a plurality of ports for data to be transmitted to a destination device, with each port being associated with a transmission data rate. The transmitter apparatus comprises processing circuitry configured to obtain data to be transmitted to the destination device via the plurality of ports. The processing circuitry is configured to multiplex the data to be transmitted to the destination device according to a weighted round-robin scheme to generate a multiplexed data stream. The weights of the weighted round-robin scheme are based on the transmission data rate of the respective port the data is obtained over. The processing circuitry is configured to transmit the multiplexed data stream to the destination device.
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公开(公告)号：US20240121185A1
公开(公告)日：2024-04-11
申请号：US18484428
申请日：2023-10-10
Applicant: MaxLinear, Inc.
Inventor： Isaac Sitton , Ingo Volkening , Oren Bakshe
CPC classification number: H04L45/566 , H04L45/42
Abstract: A network processing system includes an interface connection to obtain a packet. The network processing system also includes one or more packet processing components individually connected to a system communication channel. The one or more packet processing components are individually configured to perform a packet processing operation to the packet. The network processing system also includes a queueing system connected to the system communication channel. The queueing system determines a processing path of the packet from the interface connection and through the one or more packet processing components. The one or more packet processing components are individually configured to direct the packet to a next component using the processing path.
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公开(公告)号：US11550877B2
公开(公告)日：2023-01-10
申请号：US15303852
申请日：2015-04-15
Applicant: MaxLinear, Inc.
Inventor： Ingo Volkening , Ritesh Banerjee , Olaf Wachendorf , Stephan Pruecklmayer
Abstract: First transistor logic is arranged by a first logic provider in circuit form and provides a minimum of functionality of the semiconductor device employed to bring up the semiconductor device, wherein the minimum of functionality is encrypted using a first encryption key. Second transistor logic is arranged by a second logic provider, different than the first logic provider, in circuit form to include security keys capable to perform cryptographic capabilities using a second encryption key. The second transistor logic further includes functionality that completes the semiconductor device as a chip device and is ready to process secure communication signals.
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公开(公告)号：US12191986B2
公开(公告)日：2025-01-07
申请号：US17597647
申请日：2020-07-23
Applicant: MAXLINEAR, INC.
Inventor： Chun Feng Hu , Ingo Volkening
Abstract: Various examples of the present disclosure relate to a transmitter apparatus, device, method, and computer program, to a receiver apparatus, device, method, and computer program, and to corresponding source and destination devices and communication devices. The transmitter apparatus comprises a plurality of ports for data to be transmitted to a destination device, with each port being associated with a transmission data rate. The transmitter apparatus comprises processing circuitry configured to obtain data to be transmitted to the destination device via the plurality of ports. The processing circuitry is configured to multiplex the data to be transmitted to the destination device according to a weighted round-robin scheme to generate a multiplexed data stream. The weights of the weighted round-robin scheme are based on the transmission data rate of the respective port the data is obtained over. The processing circuitry is configured to transmit the multiplexed data stream to the destination device.
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公开(公告)号：US11153222B2
公开(公告)日：2021-10-19
申请号：US16410112
申请日：2019-05-13
Applicant: MAXLINEAR, INC.
Inventor： Ingo Volkening , Hak Keong Sim , Ritesh Banerjee
IPC: H04L12/863 , H04L12/935 , H04L12/721 , H04L12/933 , H04L29/06 , H04L12/54 , H04L29/08
Abstract: An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.
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