公开(公告)号：US20160365859A1

公开(公告)日：2016-12-15

申请号：US14862520

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fei Song ,  Osama Shana'a ,  Yuen Hui Chee

IPC: H03K19/0185 ,  H04B1/40

CPC classification number: H03K19/018514 ,  H03F3/195 ,  H03F3/3001 ,  H03F3/3028 ,  H03F3/3033 ,  H03F3/3037 ,  H03F3/45201 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/21 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/498 ,  H03F2200/69 ,  H03F2200/75 ,  H03F2203/45136 ,  H03F2203/45168 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45301 ,  H03F2203/45496 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45656 ,  H03F2203/45674 ,  H04B1/40 ,  H04B2001/0425

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract translation: 呈现低输出阻抗的宽带高线性缓冲电路包括第一PFET（PFET1），第二PFET（PFET2），第一NFET（NFET1）和第二NFET（NFET2）。 PFET1和PFET2的源极耦合到VDD。 PFET1的漏极耦合到输出引线。 PFET2作为电流源。 NFET1的漏极耦合到PFET2的漏极和PFET1的栅极。 NFET1的源极耦合到输出引线。 NFET2的源极耦合到地。 NFET2的漏极耦合到NFET1的源极和输出引线。 NFET1的栅极与第一个输入引线交流耦合。 在单端输入示例中，NFET2的栅极是交流耦合NFET1的漏极。 在差分输入示例中，NFET2的栅极被AC耦合到第二输入引线。 在另一个差分输入示例中，PFET2不仅仅是电流源，而是PFET2的栅极与第一个输入引线交流耦合。

公开(公告)号：US09893728B2

公开(公告)日：2018-02-13

申请号：US14862520

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fei Song ,  Osama Shana'a ,  Yuen Hui Chee

IPC: H03B1/00 ,  H03K19/0185 ,  H03F3/195 ,  H03F3/45 ,  H03F3/50 ,  H04B1/40 ,  H03F3/30 ,  H04B1/04

CPC classification number: H03K19/018514 ,  H03F3/195 ,  H03F3/3001 ,  H03F3/3028 ,  H03F3/3033 ,  H03F3/3037 ,  H03F3/45201 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/21 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/498 ,  H03F2200/69 ,  H03F2200/75 ,  H03F2203/45136 ,  H03F2203/45168 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45301 ,  H03F2203/45496 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45656 ,  H03F2203/45674 ,  H04B1/40 ,  H04B2001/0425

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.