公开(公告)号：US20160344086A1

公开(公告)日：2016-11-24

申请号：US14862489

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fatih Golcuk ,  Yuen Hui Chee ,  Osama K.A. Shana'a

IPC: H01P5/18 ,  H03H7/38 ,  H03F3/19 ,  H03F3/60

CPC classification number: H01P5/18 ,  H01P5/185 ,  H03F3/19 ,  H03F3/211 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/60 ,  H03F3/602 ,  H03F2200/198 ,  H03F2200/451 ,  H03F2203/45481 ,  H03H7/21 ,  H03H7/38 ,  H03H7/48

Abstract: The isolated port of a 0/90 degree coupler is terminated by a novel complex termination impedance circuit having a reactance. The absolute value of the reactance is at least two ohms. The coupler receives a signal on its input port, and outputs a first signal on its first output port and a second signal on its second output port. A first load is coupled to the first output port without an intervening matching network. A substantial impedance mismatch exists between the first output port and the first load. A second load is coupled to the second output port without an intervening matching network. A substantial impedance mismatch exists between the second output port and the second load. Despite the substantial impedance mismatches, the first and second signals have a phase difference in a range of from 88 degrees to 92 degrees while exhibiting an amplitude imbalance less than 2 dB.

Abstract translation: 0/90度耦合器的隔离端口由具有电抗的新型复合终端阻抗电路终止。 电抗的绝对值至少为2欧姆。 耦合器在其输入端口接收信号，并在其第一输出端口输出第一信号，并在其第二输出端口输出第二信号。 第一负载耦合到第一输出端口，而没有中间的匹配网络。 在第一输出端口和第一负载之间存在实质的阻抗失配。 第二负载耦合到第二输出端口，而没有中间的匹配网络。 在第二输出端口和第二负载之间存在实质的阻抗失配。 尽管存在明显的阻抗不匹配，但是第一和第二信号在88度至92度的范围内具有相位差，同时具有小于2dB的幅度不平衡。

公开(公告)号：US09787352B2

公开(公告)日：2017-10-10

申请号：US14715134

申请日：2015-05-18

Applicant: Mediatek Inc.

Inventor： Yuen Hui Chee ,  Albert Chia-Wen Jerng

IPC: H04B1/44 ,  H04B1/48 ,  H04B1/525

CPC classification number: H04B1/48 ,  H04B1/525 ,  Y10T29/49018

Abstract: A Radio Frequency (RF) front end system and method are disclosed. The RF front end system comprises an antenna, a matching network coupled to the antenna, a power amplifier (PA) coupled to the matching network via a port on a transmit path, a low noise amplifier (LNA) coupled to the matching network via the port on a receive path and at least one transmit/receive switch (T/R SW) coupled between the port and at least one of the PA and LNA.

公开(公告)号：US20160365859A1

公开(公告)日：2016-12-15

申请号：US14862520

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fei Song ,  Osama Shana'a ,  Yuen Hui Chee

IPC: H03K19/0185 ,  H04B1/40

CPC classification number: H03K19/018514 ,  H03F3/195 ,  H03F3/3001 ,  H03F3/3028 ,  H03F3/3033 ,  H03F3/3037 ,  H03F3/45201 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/21 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/498 ,  H03F2200/69 ,  H03F2200/75 ,  H03F2203/45136 ,  H03F2203/45168 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45301 ,  H03F2203/45496 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45656 ,  H03F2203/45674 ,  H04B1/40 ,  H04B2001/0425

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract translation: 呈现低输出阻抗的宽带高线性缓冲电路包括第一PFET（PFET1），第二PFET（PFET2），第一NFET（NFET1）和第二NFET（NFET2）。 PFET1和PFET2的源极耦合到VDD。 PFET1的漏极耦合到输出引线。 PFET2作为电流源。 NFET1的漏极耦合到PFET2的漏极和PFET1的栅极。 NFET1的源极耦合到输出引线。 NFET2的源极耦合到地。 NFET2的漏极耦合到NFET1的源极和输出引线。 NFET1的栅极与第一个输入引线交流耦合。 在单端输入示例中，NFET2的栅极是交流耦合NFET1的漏极。 在差分输入示例中，NFET2的栅极被AC耦合到第二输入引线。 在另一个差分输入示例中，PFET2不仅仅是电流源，而是PFET2的栅极与第一个输入引线交流耦合。

公开(公告)号：US09893728B2

公开(公告)日：2018-02-13

申请号：US14862520

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fei Song ,  Osama Shana'a ,  Yuen Hui Chee

IPC: H03B1/00 ,  H03K19/0185 ,  H03F3/195 ,  H03F3/45 ,  H03F3/50 ,  H04B1/40 ,  H03F3/30 ,  H04B1/04

CPC classification number: H03K19/018514 ,  H03F3/195 ,  H03F3/3001 ,  H03F3/3028 ,  H03F3/3033 ,  H03F3/3037 ,  H03F3/45201 ,  H03F3/45475 ,  H03F3/505 ,  H03F2200/21 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/498 ,  H03F2200/69 ,  H03F2200/75 ,  H03F2203/45136 ,  H03F2203/45168 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45301 ,  H03F2203/45496 ,  H03F2203/45544 ,  H03F2203/45596 ,  H03F2203/45656 ,  H03F2203/45674 ,  H04B1/40 ,  H04B2001/0425

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

公开(公告)号：US09806394B2

公开(公告)日：2017-10-31

申请号：US14862489

申请日：2015-09-23

Applicant: MEDIATEK INC.

Inventor： Fatih Golcuk ,  Yuen Hui Chee ,  Osama K. A. Shana'a

IPC: H01P5/12 ,  H03H7/38 ,  H01P5/18 ,  H03F3/60 ,  H03H7/21 ,  H03H7/48 ,  H03F3/19 ,  H03F3/21 ,  H03F3/45

CPC classification number: H01P5/18 ,  H01P5/185 ,  H03F3/19 ,  H03F3/211 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/60 ,  H03F3/602 ,  H03F2200/198 ,  H03F2200/451 ,  H03F2203/45481 ,  H03H7/21 ,  H03H7/38 ,  H03H7/48

Abstract: The isolated port of a 0/90 degree coupler is terminated by a novel complex termination impedance circuit having a reactance. The absolute value of the reactance is at least two ohms. The coupler receives a signal on its input port, and outputs a first signal on its first output port and a second signal on its second output port. A first load is coupled to the first output port without an intervening matching network. A substantial impedance mismatch exists between the first output port and the first load. A second load is coupled to the second output port without an intervening matching network. A substantial impedance mismatch exists between the second output port and the second load. Despite the substantial impedance mismatches, the first and second signals have a phase difference in a range of from 88 degrees to 92 degrees while exhibiting an amplitude imbalance less than 2 dB.