公开(公告)号：US10936006B1

公开(公告)日：2021-03-02

申请号：US16557290

申请日：2019-08-30

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Charles R. Ruelke ,  Johnny R. Ferreira

IPC: G06F1/08 ,  G06F1/324 ,  G06F1/3237

Abstract: Clock distribution network and method for dynamically changing clock frequency in digital processing system are provided. The method includes receiving, at a first clock input of a first divider, a frequency signal from a clock source and receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider. The method includes asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted and after asserting the first hold signal, latching a new first divider value into the first divider. The method includes de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.

公开(公告)号：US11036506B1

公开(公告)日：2021-06-15

申请号：US16710862

申请日：2019-12-11

Applicant: Motorola Solutions, Inc.

Inventor： Jerry Redington ,  Johnny R. Ferreira ,  Charles R. Ruelke

IPC: G06F9/30

Abstract: Some example memory systems include a load and store unit (LSU) operable to load a memory reference. The LSU may include an alignment register, a current memory reference register, and a vector register. The memory system may include a memory coupled to the LSU. The memory may be operable to store a memory reference. The memory reference may be aligned or unaligned in the memory, and the LSU may be operable to efficiently load both unaligned and aligned memory references. Some example memory systems include a load and store unit (LSU) operable to store to the memory at a memory address. The LSU may be operable to efficiently store to both unaligned and aligned memory addresses. The LSU may perform loads and stores in forward and reverse stride.

公开(公告)号：US09735759B1

公开(公告)日：2017-08-15

申请号：US15095644

申请日：2016-04-11

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Edward A. Diaz ,  Johnny R. Ferreira ,  Ricardo Franco ,  Charles R. Ruelke ,  Richard S. Young

IPC: H03K3/00 ,  H03K3/013 ,  H03K3/66 ,  H03K5/1534

CPC classification number: H03K3/013 ,  H03K3/66 ,  H03K5/1534 ,  H03K19/00346 ,  H03M1/0818 ,  H03M1/0872 ,  H03M1/12

Abstract: A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

公开(公告)号：US20210182063A1

公开(公告)日：2021-06-17

申请号：US16710862

申请日：2019-12-11

Applicant: Motorola Solutions, Inc.

Inventor： Jerry Redington ,  Johnny R. Ferreira ,  Charles R. Ruelke

IPC: G06F9/30

Abstract: Some example memory systems include a load and store unit (LSU) operable to load a memory reference. The LSU may include an alignment register, a current memory reference register, and a vector register. The memory system may include a memory coupled to the LSU. The memory may be operable to store a memory reference. The memory reference may be aligned or unaligned in the memory, and the LSU may be operable to efficiently load both unaligned and aligned memory references. Some example memory systems include a load and store unit (LSU) operable to store to the memory at a memory address. The LSU may be operable to efficiently store to both unaligned and aligned memory addresses. The LSU may perform loads and stores in forward and reverse stride.

公开(公告)号：US20210064075A1

公开(公告)日：2021-03-04

申请号：US16557290

申请日：2019-08-30

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Charles R. Ruelke ,  Johnny R. Ferreira

IPC: G06F1/08 ,  G06F1/3237 ,  H03L7/18 ,  G06F1/324

Abstract: Clock distribution network and method for dynamically changing clock frequency in digital processing system are provided. The method includes receiving, at a first clock input of a first divider, a frequency signal from a clock source and receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider. The method includes asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted and after asserting the first hold signal, latching a new first divider value into the first divider. The method includes de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.

公开(公告)号：US10573360B1

公开(公告)日：2020-02-25

申请号：US16204698

申请日：2018-11-29

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Johnny R. Ferreira ,  Charles R. Ruelke

IPC: G11C8/18 ,  G11C7/22 ,  G06F1/04 ,  G11C7/10 ,  G11C11/4076 ,  G11C29/02

Abstract: A method and apparatus for adaptable phase training of high frequency clock signaling for data capture is provided. A state machine synchronizes a first selection signal to a delay multiplexer and a second selection signal to a digital block demultiplexer to sequentially select a targeted pair of the static storage elements for each of a plurality of phase-delayed data strobe clock signals. Read back data from an external memory captured by the static storage elements is compared to known valid data. The state machine determines which of the plurality of phase-delayed data strobe clock signals resulted in known valid data being captured by the static storage elements based on the comparison. The state machine selects one of the plurality of phase-delayed data strobe clock signals that resulted in valid data being captured as a read clock signal for a memory controller to capture subsequent read data from the external memory.

公开(公告)号：US09514066B1

公开(公告)日：2016-12-06

申请号：US14849535

申请日：2015-09-09

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Edward A. Diaz ,  Johnny R. Ferreira ,  Ricardo Franco ,  Charles R. Ruelke ,  Matthew E. Simms

IPC: G06F3/00 ,  G06F13/10 ,  G06F13/20 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/20 ,  G06F13/4068

Abstract: A real-time reconfigurable input/output interface of a controller and a method of reconfiguring the same. The reconfigurable interface enables the controller to communicate with a plurality of peripheral digital subsystem blocks, and includes an input/output interface, a profile memory, and a state machine. The input/output interface includes a plurality of data lines including a shared portion that are shared among the plurality of peripheral digital subsystem blocks. The profile memory stores a plurality of interface profiles, each interface profile defining a configuration of the input/output interface to communicate with an associated one of the peripheral blocks. The state machine is coupled to the profile memory to receive interface profiles and to the input/output interface. In response to each request to communicate with a particular peripheral block, the state machine configures the input/output interface according to the interface profile associated with the particular peripheral block.

Abstract translation: 控制器的实时可重配置输入/输出接口和重新配置控制器的方法。 可重配置接口使得控制器能够与多个外围数字子系统块进行通信，并且包括输入/​​输出接口，简档存储器和状态机。 输入/输出接口包括多个数据线，包括在多个外围数字子系统块之间共享的共享部分。 简档存储器存储多个接口配置文件，每个接口配置文件定义了输入/输出接口的配置，以便与相关联的外围块之一进行通信。 状态机耦合到配置文件存储器以接收接口配置文件和输入/输出接口。 响应于与特定外围块通信的每个请求，状态机根据与特定外围块相关联的接口配置来配置输入/输出接口。