公开(公告)号：US09735759B1

公开(公告)日：2017-08-15

申请号：US15095644

申请日：2016-04-11

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Edward A. Diaz ,  Johnny R. Ferreira ,  Ricardo Franco ,  Charles R. Ruelke ,  Richard S. Young

IPC: H03K3/00 ,  H03K3/013 ,  H03K3/66 ,  H03K5/1534

CPC classification number: H03K3/013 ,  H03K3/66 ,  H03K5/1534 ,  H03K19/00346 ,  H03M1/0818 ,  H03M1/0872 ,  H03M1/12

Abstract: A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

公开(公告)号：US09514066B1

公开(公告)日：2016-12-06

申请号：US14849535

申请日：2015-09-09

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Edward A. Diaz ,  Johnny R. Ferreira ,  Ricardo Franco ,  Charles R. Ruelke ,  Matthew E. Simms

IPC: G06F3/00 ,  G06F13/10 ,  G06F13/20 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/20 ,  G06F13/4068

Abstract: A real-time reconfigurable input/output interface of a controller and a method of reconfiguring the same. The reconfigurable interface enables the controller to communicate with a plurality of peripheral digital subsystem blocks, and includes an input/output interface, a profile memory, and a state machine. The input/output interface includes a plurality of data lines including a shared portion that are shared among the plurality of peripheral digital subsystem blocks. The profile memory stores a plurality of interface profiles, each interface profile defining a configuration of the input/output interface to communicate with an associated one of the peripheral blocks. The state machine is coupled to the profile memory to receive interface profiles and to the input/output interface. In response to each request to communicate with a particular peripheral block, the state machine configures the input/output interface according to the interface profile associated with the particular peripheral block.

Abstract translation: 控制器的实时可重配置输入/输出接口和重新配置控制器的方法。 可重配置接口使得控制器能够与多个外围数字子系统块进行通信，并且包括输入/​​输出接口，简档存储器和状态机。 输入/输出接口包括多个数据线，包括在多个外围数字子系统块之间共享的共享部分。 简档存储器存储多个接口配置文件，每个接口配置文件定义了输入/输出接口的配置，以便与相关联的外围块之一进行通信。 状态机耦合到配置文件存储器以接收接口配置文件和输入/输出接口。 响应于与特定外围块通信的每个请求，状态机根据与特定外围块相关联的接口配置来配置输入/输出接口。

公开(公告)号：US09602115B1

公开(公告)日：2017-03-21

申请号：US15174871

申请日：2016-06-06

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Mark Rozental ,  Ricardo Franco ,  Claudine Tordjman ,  Richard S. Young

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/093 ,  H03L7/095 ,  H03L7/089 ,  H03K5/15 ,  H03L7/18

CPC classification number: H03L7/0996 ,  H03K5/15046 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/1806

Abstract: A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.