公开(公告)号：US07089160B2

公开(公告)日：2006-08-08

申请号：US10042539

申请日：2002-01-08

Applicant: Manh-Quan Tam Nguyen

Inventor： Manh-Quan Tam Nguyen

IPC: G06F17/10

CPC classification number: H05K3/4638 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/0047 ,  H05K2201/09918

Abstract: A method of creating a mathematical model which is employed in the determination of at least one work location in a multi-layered laminated circuit panel. The mathematical model for modifying drill data takes into consideration translational and rotational compensations caused by the encountered stretching or shrinking of the multi-layered panel subsequent to pressing or due to thermally processing, whereby the mathematical model may be utilized to modify drill data in order to accurately predict hole or via locations.

公开(公告)号：US07084509B2

公开(公告)日：2006-08-01

申请号：US10263909

申请日：2002-10-03

Applicant: Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

Inventor： Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract translation: 通过在层叠到用作接地平面或电源平面的导电金属芯的第一介电层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。 通过延伸到芯的电介质层提供孔。 使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。 金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。 第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。 该第二通孔可以由常规电镀技术形成。 可以以这种方式组装具有堆叠的盲孔的多个电介质层。

公开(公告)号：US06924224B2

公开(公告)日：2005-08-02

申请号：US10729174

申请日：2003-12-05

Applicant: Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

Inventor： Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46 ,  H01L21/4762 ,  H01L21/44

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract translation: 通过在层叠到用作接地平面或电源平面的导电金属芯的第一电介质层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。 通过延伸到芯的电介质层提供孔。 使用金属芯作为阴极电解沉积诸如铜的金属，或者化学镀而不接合到孔中。 金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。 第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。 该第二通孔可以由常规电镀技术形成。 可以以这种方式组装具有堆叠的盲孔的多个电介质层。