公开(公告)号：US20180146550A1

公开(公告)日：2018-05-24

申请号：US15557438

申请日：2016-03-11

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Markus MAIER

IPC: H05K1/05 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/44

CPC classification number: H05K1/05 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/053 ,  H05K1/056 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/445 ,  H05K3/46 ,  H05K3/4608 ,  H05K2201/09509 ,  H05K2201/09554

Abstract: A printed circuit board is provided which comprises a core layer of a conductive metal having a thickness between 30 micrometer and 120 micrometer, an upper dielectric layer and a lower dielectric layer sandwiching the core layer; an upper conductive layer arranged above the upper dielectric layer and a lower conductive layer arranged below the lower dielectric layer; at least one via passing from the upper conductive layer to the lower conductive layer and filled at least partially with the dielectric material of the upper and/or lower dielectric layer; and at least one and blind via, connecting the upper conductive layer with the core layer.

公开(公告)号：US09648742B2

公开(公告)日：2017-05-09

申请号：US15105723

申请日：2014-10-14

Applicant: Auto-Kabel Management GmbH

Inventor： Wacim Tazarine ,  Simon Betscher ,  Frank Gronwald

IPC: H05K7/10 ,  H05K1/14 ,  H05K1/05 ,  H05K3/36 ,  H05K7/00 ,  H05K1/16 ,  H05K1/18 ,  H05K3/28 ,  H01L23/14 ,  C23C14/04 ,  H01L23/367 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/145 ,  C23C14/042 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/056 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K1/181 ,  H05K1/182 ,  H05K3/28 ,  H05K3/282 ,  H05K3/368 ,  H05K2201/09372 ,  H05K2201/09554 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2203/1377 ,  H01L2924/00

Abstract: Circuit having a first printed circuit board and a second printed circuit board. In the circuit, the printed circuit boards spaced apart from one another by means of an air gap are mechanically connected together by at least one power semiconductor.

公开(公告)号：US20140126169A1

公开(公告)日：2014-05-08

申请号：US14062264

申请日：2013-10-24

Applicant: NITTO DENKO CORPORATION

Inventor： Terukazu IHARA ,  Jun ISHII ,  Naohiro TERADA

IPC: H05K7/02 ,  H05K3/10

CPC classification number: H05K3/10 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/4685 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: A plurality of suspension boards and an inspection substrate are integrally supported by a support frame. In each suspension board, a line is formed on a conductive first support substrate via a first insulating layer. The first support substrate and the line are electrically connected by a first via in the first insulating layer. In the inspection substrate, a conductor layer is formed on a conductive second support substrate with a second insulating layer sandwiched therebetween. The second support substrate and the conductor layer are electrically connected by a second via in the second insulating layer. The first via and the second via have the same configuration.

Abstract translation: 多个悬挂板和检查基板由支撑框架一体地支撑。 在每个悬挂板中，经由第一绝缘层在导电的第一支撑基板上形成线。 第一支撑基板和线通过第一绝缘层中的第一通孔电连接。 在检查基板中，导电层形成在导电性的第二支撑基板上，其间夹着第二绝缘层。 第二支撑基板和导体层通过第二绝缘层中的第二通孔电连接。 第一通孔和第二通孔具有相同的配置。

公开(公告)号：US20120090878A1

公开(公告)日：2012-04-19

申请号：US13303769

申请日：2011-11-23

Applicant: Yoichi HITOMI ,  Hiroaki MIYAZAWA ,  Shinji KUMON ,  Terutoshi MOMOSE

Inventor： Yoichi HITOMI ,  Hiroaki MIYAZAWA ,  Shinji KUMON ,  Terutoshi MOMOSE

IPC: H05K1/00

CPC classification number: G06F1/182 ,  G11B5/40 ,  G11B5/484 ,  G11B5/4853 ,  H05K1/0215 ,  H05K1/056 ,  H05K1/116 ,  H05K3/44 ,  H05K2201/09463 ,  H05K2201/09554

Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.

Abstract translation: 悬浮基板包括金属基板，形成在金属基板上的绝缘层，具有用于接地端子的开口和形成在绝缘层上的接地导体。 接地端子形成材料放置在接地端子的开口中，形成连接金属基板和接地导体的接地端子。 接地导体不包围用于接地端子的开口的圆周的一部分。

公开(公告)号：US08110909B1

公开(公告)日：2012-02-07

申请号：US12655724

申请日：2010-01-05

Applicant: David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

Inventor： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

IPC: H01L23/02

CPC classification number: H01L24/73 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1815 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/423 ,  H05K7/1061 ,  H05K2201/09036 ,  H05K2201/09554 ,  H05K2203/0723 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.

Abstract translation: 包括用于安装另一半导体封装的顶表面端子的半导体封装提供三维电路配置，其可以提供具有标准设计的现有格栅阵列封装的可移除连接。 半导体管芯安装在电连接到具有设置在底侧的端子的电路基板上，用于连接到外部系统。 封装裸片和衬底，并且将通孔激光烧蚀或以其它形式通过封装形成到衬底的顶表面上的端子，其提供可安装另一个栅格阵列半导体封装的栅格阵列安装焊盘。 通孔的底侧可以终止并电连接到基板上的端子，半导体封装的底部的端子（通过端子）或半导体管芯的顶部上的端子。 通孔可以被电镀，糊状填充，填充低熔点合金，并且可以具有锥形轮廓以改善电镀性能。

公开(公告)号：US08097811B2

公开(公告)日：2012-01-17

申请号：US12062730

申请日：2008-04-04

Applicant: Yoichi Hitomi ,  Hiroaki Miyazawa ,  Shinji Kumon ,  Terutoshi Momose

Inventor： Yoichi Hitomi ,  Hiroaki Miyazawa ,  Shinji Kumon ,  Terutoshi Momose

IPC: H05K1/00 ,  H05K1/02

CPC classification number: G06F1/182 ,  G11B5/40 ,  G11B5/484 ,  G11B5/4853 ,  H05K1/0215 ,  H05K1/056 ,  H05K1/116 ,  H05K3/44 ,  H05K2201/09463 ,  H05K2201/09554

Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.

Abstract translation: 悬浮基板包括金属基板，形成在金属基板上的绝缘层，具有用于接地端子的开口和形成在绝缘层上的接地导体。 接地端子形成材料放置在接地端子的开口中，形成连接金属基板和接地导体的接地端子。 接地导体不包围用于接地端子的开口的圆周的一部分。

公开(公告)号：US08065795B2

公开(公告)日：2011-11-29

申请号：US11760217

申请日：2007-06-08

Applicant: Kevin C. Olson ,  Alan G. Wang

Inventor： Kevin C. Olson ,  Alan G. Wang

IPC: H01K3/22

CPC classification number: H01L21/486 ,  C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上涂一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：US08044341B2

公开(公告)日：2011-10-25

申请号：US12384833

申请日：2009-04-09

Applicant: Tomihisa Saito

Inventor： Tomihisa Saito

IPC: H01J40/14

CPC classification number: H05K1/0203 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/05 ,  H05K3/3442 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/10106 ,  H01L2924/00014

Abstract: An electronic component capable of effectively dissipating heat generated in an LED chip and other elements is provided. A light emitting unit 1 includes a substrate 2 made of copper or aluminum, an insulating layer 3 formed on the surface thereof, a circuit pattern 4 formed on the insulating layer 3, and a circuit pattern 5 formed on the substrate 2 through an opening 3a that has been formed in advance in the insulation layer 3. An LED chip 6 is mounted on the circuit patterns 4 and 5 by using solder 7. The LED chip 6 includes a ceramic substrate 9, electrodes 10 and 11 formed thereon, and an LED die 12 as a light emitting portion disposed on the electrode 11, which is one of the electrodes. Terminals 13 and 14 are provided on the upper surface of the LED die 12. The terminal 13, which is one of the terminals, is connected to the electrode 10 via a bonding wire 15, and the terminal 14, which is the other one of the terminals, is connected to the electrode 11 via a bonding wire 16.

Abstract translation: 提供能够有效地散发在LED芯片和其他元件中产生的热的电子部件。 发光单元1包括由铜或铝制成的基板2，形成在其表面上的绝缘层3，形成在绝缘层3上的电路图案4和通过开口3a形成在基板2上的电路图案5 预先形成在绝缘层3中。通过使用焊料7将LED芯片6安装在电路图案4,5上.LED芯片6包括陶瓷基板9，形成在其上的电极10和11以及LED 管芯12作为发光部分，设置在作为电极之一的电极11上。 端子13和14设置在LED管芯12的上表面上。作为端子之一的端子13通过接合线15连接到电极10，端子14是另一个 端子经由接合线16连接到电极11。

公开(公告)号：US08026587B1

公开(公告)日：2011-09-27

申请号：US12802661

申请日：2010-06-10

Applicant: David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

Inventor： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

IPC: H01L23/22

CPC classification number: H01L24/73 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1815 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/423 ,  H05K7/1061 ,  H05K2201/09036 ,  H05K2201/09554 ,  H05K2203/0723 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste- filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.

Abstract translation: 包括用于安装另一半导体封装的顶表面端子的半导体封装提供三维电路配置，其可以提供具有标准设计的现有格栅阵列封装的可移除连接。 半导体管芯安装在电连接到具有设置在底侧的端子的电路基板上，用于连接到外部系统。 封装裸片和衬底，并且将通孔激光烧蚀或以其它形式通过封装形成到衬底的顶表面上的端子，其提供可安装另一个栅格阵列半导体封装的栅格阵列安装焊盘。 通孔的底侧可以终止并电连接到基板上的端子，半导体封装的底部的端子（通过端子）或半导体管芯的顶部上的端子。 通孔可以镀覆，糊状填充，填充低熔点合金，并且可以具有锥形轮廓以改善电镀性能。

公开(公告)号：US08008188B2

公开(公告)日：2011-08-30

申请号：US11760804

申请日：2007-06-11

Applicant: Kevin C. Olson ,  Alan E. Wang

Inventor： Kevin C. Olson ,  Alan E. Wang

IPC: H01L21/4763

CPC classification number: H05K3/44 ,  H05K3/108 ,  H05K3/388 ,  H05K3/445 ,  H05K3/4647 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/0733 ,  H05K2203/135

Abstract: A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.

Abstract translation: 提供了一种方法，包括：用第一可移除材料涂覆导电芯，在第一可移除材料中形成开口以暴露部分导电芯，将导电材料镀在导电芯的暴露部分上， 具有第二可移除材料的材料，去除第一可移除材料，用电介质涂层电泳涂覆导电芯，以及去除第二可除去材料。