公开(公告)号：US20240356681A1

公开(公告)日：2024-10-24

申请号：US18762573

申请日：2024-07-02

Applicant: MaxLinear, Inc.

Inventor： Ingo Volkening ,  Amos Klimker ,  Rafi Abraham

IPC: H04L1/1829 ,  H04L1/1607

CPC classification number: H04L1/1841 ,  H04L1/1642

Abstract: A system may include primary and secondary integrated circuits. The primary integrated circuit may receive a first subset of data packets associated with a first set of sequence numbers. The secondary integrated circuit may receive a second subset of data packets associated with a second set of sequence numbers. The primary integrated circuit is configured to manage the first set of sequence numbers and the second set of sequence numbers on behalf of the secondary integrated circuit and for the system.

公开(公告)号：US20230216584A1

公开(公告)日：2023-07-06

申请号：US18146970

申请日：2022-12-27

Applicant: MaxLinear, Inc.

Inventor： Gerfried Krampl ,  Barak Hermesh ,  Amos Klimker ,  Shaul Shulman ,  Franz-Josef Schaefer ,  Guy Ray

IPC: H04B10/25 ,  H04B10/27 ,  H04B10/40

CPC classification number: H04B10/25 ,  H04B10/27 ,  H04B10/40 ,  H04L63/0428

Abstract: A network infrastructure combining data over cable service interface specification (DOCSIS) cable modem management and 10 Gb passive optical network XGPON networking technology. The DOCSIS equipment controls restrict the XGPON to physical layer (layer 1) while the DOCSIS equipment operate at a data link layer and above.

公开(公告)号：US12057881B2

公开(公告)日：2024-08-06

申请号：US18146970

申请日：2022-12-27

Applicant: MaxLinear, Inc.

Inventor： Gerfried Krampl ,  Barak Hermesh ,  Amos Klimker ,  Shaul Shulman ,  Franz-Josef Schaefer ,  Guy Ray

IPC: H04J14/00 ,  H04B10/25 ,  H04B10/27 ,  H04B10/40 ,  H04L9/40

CPC classification number: H04B10/25 ,  H04B10/27 ,  H04B10/40 ,  H04L63/0428

Abstract: A network infrastructure combining data over cable service interface specification (DOCSIS) cable modem management and 10 Gb passive optical network XGPON networking technology. The DOCSIS equipment controls restrict the XGPON to physical layer (layer 1) while the DOCSIS equipment operate at a data link layer and above.

公开(公告)号：US20240396635A1

公开(公告)日：2024-11-28

申请号：US18795157

申请日：2024-08-05

Applicant: MaxLinear, Inc.

Inventor： Gerfried Krampl ,  Barak Hermesh ,  Amos Klimker ,  Shaul Shulman ,  Franz-Josef Schäfer ,  Guy Ray

IPC: H04B10/25 ,  H04B10/27 ,  H04B10/40 ,  H04L9/40

Abstract: A network infrastructure combining data over cable service interface specification (DOCSIS) cable modem management and 10 Gb passive optical network XGPON networking technology. The DOCSIS equipment controls restrict the XGPON to physical layer (layer 1) while the DOCSIS equipment operate at a data link layer and above.

公开(公告)号：US12028168B2

公开(公告)日：2024-07-02

申请号：US17659281

申请日：2022-04-14

Applicant: MAXLINEAR, INC.

Inventor： Ingo Volkening ,  Amos Klimker ,  Rafi Abraham

IPC: H04L1/1829 ,  H04L1/1607

CPC classification number: H04L1/1841 ,  H04L1/1642

Abstract: A system may include primary and secondary integrated circuits. The primary integrated circuit may receive a first subset of data packets associated with a first set of sequence numbers. The secondary integrated circuit may receive a second subset of data packets associated with a second set of sequence numbers. The primary integrated circuit is configured to manage the first set of sequence numbers and the second set of sequence numbers on behalf of the secondary integrated circuit and for the system.

公开(公告)号：US20220337354A1

公开(公告)日：2022-10-20

申请号：US17659281

申请日：2022-04-14

Applicant: MAXLINEAR, INC.

Inventor： Ingo Volkening ,  Amos Klimker ,  Rafi Abraham

IPC: H04L1/18 ,  H04L1/16

Abstract: A system may include primary and secondary integrated circuits. The primary integrated circuit may receive a first subset of data packets associated with a first set of sequence numbers. The secondary integrated circuit may receive a second subset of data packets associated with a second set of sequence numbers. The primary integrated circuit is configured to manage the first set of sequence numbers and the second set of sequence numbers on behalf of the secondary integrated circuit and for the system.