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公开(公告)号：US09576614B2
公开(公告)日：2017-02-21
申请号：US14450324
申请日：2014-08-04
Applicant: MaxLinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
CPC classification number: G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
Abstract translation: 一种用于存储器功率和/或面积减小的方法和装置。 可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。 可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。 灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。 附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。
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公开(公告)号：US20190139584A1
公开(公告)日：2019-05-09
申请号：US16237396
申请日：2018-12-31
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
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Patent Agency Ranking
公开(公告)号：US10176850B2
公开(公告)日：2019-01-08
申请号：US15880913
申请日：2018-01-26
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
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公开(公告)号：US20180151202A1
公开(公告)日：2018-05-31
申请号：US15880913
申请日：2018-01-26
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
CPC classification number: G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
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公开(公告)号：US20170162233A1
公开(公告)日：2017-06-08
申请号：US15434715
申请日：2017-02-16
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
CPC classification number: G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
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公开(公告)号：US20150023122A1
公开(公告)日：2015-01-22
申请号：US14450324
申请日：2014-08-04
Applicant: MaxLinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
IPC: G11C5/14
CPC classification number: G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
Abstract translation: 一种用于存储器功率和/或面积减小的方法和装置。 可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。 可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。 灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。 附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。
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公开(公告)号：US09881653B2
公开(公告)日：2018-01-30
申请号：US15434715
申请日：2017-02-16
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Vadim Smolyakov , Timothy Gallagher , Glenn Gulak
CPC classification number: G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
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