公开(公告)号：US10020247B2

公开(公告)日：2018-07-10

申请号：US14950865

申请日：2015-11-24

Applicant: Maxlinear, Inc.

Inventor： Weizhong Cai ,  Kimihiko Imura ,  Wei Gu

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and systems for improved matching for on-chip capacitors may comprise in a semiconductor die comprising an on-chip capacitor with one or more metal layers: electrically coupling a first set of metal fingers, electrically coupling a second set of metal fingers that are interdigitated with the first set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are arranged symmetrically in the semiconductor die, and configuring the on-chip capacitor in a plurality of symmetric sections, wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern. The first set of metal fingers and the second set of metal fingers may be arranged with radial symmetry. A first set of metal fingers in a first metal layer may be electrically coupled to a set of metal fingers in a second metal layer.

公开(公告)号：US20180323135A1

公开(公告)日：2018-11-08

申请号：US16030397

申请日：2018-07-09

Applicant: Maxlinear, Inc.

Inventor： Weizhong Cai ,  Kimihiko Imura ,  Wei Gu

IPC: H01L23/495 ,  H01L23/522 ,  H01L49/02 ,  H01L21/48 ,  H01L27/02

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.

公开(公告)号：US20170148712A1

公开(公告)日：2017-05-25

申请号：US14950865

申请日：2015-11-24

Applicant: Maxlinear, Inc.

Inventor： Weizhong Cai ,  Kimihiko Imura ,  Wei Gu

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.