公开(公告)号：US20140301133A1

公开(公告)日：2014-10-09

申请号：US14244327

申请日：2014-04-03

Applicant: MaxLinear, Inc.

Inventor： Kimihiko Imura ,  Jianping Yang

IPC: G11C11/24

CPC classification number: G11C11/24 ,  H01L27/0207 ,  H01L27/10805

Abstract: Methods and systems for a high-density, low-cost, CMOS compatible memory may comprise a memory cell on a chip, the memory cell comprising: a plurality of capacitor/switch pairs, where for each pair comprising a switch and a capacitor, a source terminal of the switch is coupled to a gate terminal of the capacitor. The memory cell may also comprise a reset transistor, a biasing circuit, and a source follower. A drain terminal of each switch may be coupled to a floating node that couples a source terminal of the reset transistor and a gate terminal of the source follower. Drain and source terminals of each of the switches of the plurality of capacitor/switch pairs may be coupled to ground. A number of the plurality of capacitor/switch pairs may indicate a number of bits in the memory. The biasing circuit may comprise a current mirror. A bit-line for the memory cell may be coupled to a source terminal of the source follower. The bit-line may comprise a metal trace.

Abstract translation: 用于高密度，低成本的CMOS兼容存储器的方法和系统可以包括芯片上的存储器单元，所述存储单元包括：多个电容器/开关对，其中对于包括开关和电容器的每一对， 开关的源极端子耦合到电容器的栅极端子。 存储单元还可以包括复位晶体管，偏置电路和源极跟随器。 每个开关的漏极端子可以耦合到浮动节点，该浮动节点耦合复位晶体管的源极端子和源极跟随器的栅极端子。 多个电容器/开关对中的每个开关的漏极和源极端子可以耦合到地。 多个电容器/开关对中的多个可以指示存储器中的位数。 偏置电路可以包括电流镜。 存储器单元的位线可以耦合到源极跟随器的源极端子。 位线可以包括金属迹线。

公开(公告)号：US10020247B2

公开(公告)日：2018-07-10

申请号：US14950865

申请日：2015-11-24

Applicant: Maxlinear, Inc.

Inventor： Weizhong Cai ,  Kimihiko Imura ,  Wei Gu

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and systems for improved matching for on-chip capacitors may comprise in a semiconductor die comprising an on-chip capacitor with one or more metal layers: electrically coupling a first set of metal fingers, electrically coupling a second set of metal fingers that are interdigitated with the first set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are arranged symmetrically in the semiconductor die, and configuring the on-chip capacitor in a plurality of symmetric sections, wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern. The first set of metal fingers and the second set of metal fingers may be arranged with radial symmetry. A first set of metal fingers in a first metal layer may be electrically coupled to a set of metal fingers in a second metal layer.

公开(公告)号：US20180323135A1

公开(公告)日：2018-11-08

申请号：US16030397

申请日：2018-07-09

Applicant: Maxlinear, Inc.

Inventor： Weizhong Cai ,  Kimihiko Imura ,  Wei Gu

IPC: H01L23/495 ,  H01L23/522 ,  H01L49/02 ,  H01L21/48 ,  H01L27/02

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.

公开(公告)号：US20170148712A1

公开(公告)日：2017-05-25

申请号：US14950865

申请日：2015-11-24

Applicant: Maxlinear, Inc.

Inventor： Weizhong Cai ,  Kimihiko Imura ,  Wei Gu

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.