LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER

    公开(公告)号:US20190305800A1

    公开(公告)日:2019-10-03

    申请号:US16367538

    申请日:2019-03-28

    Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

    Low-power block code forward error correction decoder

    公开(公告)号:US11750223B2

    公开(公告)日:2023-09-05

    申请号:US16367538

    申请日:2019-03-28

    CPC classification number: H03M13/1545 H03M13/1105 H03M13/157 H03M13/6561

    Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

    Receiver filtering
    3.
    发明授权

    公开(公告)号:US12224855B2

    公开(公告)日:2025-02-11

    申请号:US18354580

    申请日:2023-07-18

    Inventor: Youzhe Fan

    Abstract: A receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

    LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER

    公开(公告)号:US20230412196A1

    公开(公告)日:2023-12-21

    申请号:US18461361

    申请日:2023-09-05

    CPC classification number: H03M13/1545 H03M13/6561 H03M13/157 H03M13/1105

    Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

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